Cryptography & Data Integrity

ML-KEM / Kyber NTT Accelerator

mlkemntt is the number-theoretic transform (NTT) core at the heart of post-quantum ML-KEM (Kyber, FIPS 203) and ML-DSA (Dilithium, FIPS 204).

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ASIL-B

target

91.46%

SPFM

94.30%

LFM

PASS

FMEDA

18.0K

gates

1.0.0

version

The deliverable

What you’re licensing

mlkemntt is the number-theoretic transform (NTT) core at the heart of post-quantum ML-KEM (Kyber, FIPS 203) and ML-DSA (Dilithium, FIPS 204). It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

mlkem_ntt is the number-theoretic transform (NTT) core at the heart of post-quantum ML-KEM (Kyber, FIPS 203) and ML-DSA (Dilithium, FIPS 204).

Key Features

Three ops on one shared butterfly datapath: forward Cooley-Tukey NTT, inverse Gentleman-Sande NTT (+ n⁻¹ to-Montgomery scale), and incomplete-NTT base multiply — a*b mod (x²⁵⁶+1) = INTT(BASEMUL(NTT(a),NTT(b)))
Fixed to the Kyber/ML-KEM ring for FIPS 203/204 interop: q=3329, n=256, ζ=17, Montgomery R=2¹⁶, QINV=−3327, F=1441 (mont²/128 inverse-NTT scale)
Bare compute core: no bus, no register file — direct wr_addr/rd_addr coefficient-RAM access plus an op/start/busy/done handshake, meant to sit behind a host or orchestrator sequencer
Drop-in engine for mlkem_kem’s FIPS 203 KeyGen/Encaps/Decaps orchestrator: one of five shared compute engines behind a generic LOAD → RUN → READ phase sequencer and one polynomial RAM
Bit-exact against the pq-crystals golden model (tools/mlkem_ntt_gold.py): forward NTT, the a·R round-trip, and the full a*b mod (x²⁵⁶+1) polynomial multiply all match 256/256
Control-FSM duplicate-DMR (err_code 9) plus an op-sequence parity check (err_code 1) feeding a shared safety_monitor — an ISO 26262 ASIL-B SEooC building block with DFT fault-injection ports (fi_parity/fi_dmr) to prove both mechanisms
Coefficient-RAM SECDED is a stated integrator Assumption of Use (wrap in ecc_sram, credited at its measured DC); FMEDA PASS at ASIL-B — SPFM 91.46%, LFM 94.30%, PMHF 2.90×10⁻⁸/h

Standards & Compliance

FIPS 203 (ML-KEM/Kyber) and FIPS 204 (ML-DSA/Dilithium) polynomial arithmetic, pq-crystals reference algorithms; ISO 26262 ASIL-B SEooC (SPFM 91.46%, LFM 94.30%, PMHF 2.90×10⁻⁸/h, informational Technology-Preview)

Functional Safety

ASIL-B (SEooC) · SPFM 91.46% · LFM 94.30% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
mlkem_ntt #(
  .ADDR_W(6)
) u_mlkem_ntt (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ML-KEM / Kyber NTT Accelerator?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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