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AI Inference & Acceleration

Tileable RISC-V + MAC Compute Cluster

tilecompute is a tileable compute cluster: N compute lanes — each a dual-core-lockstep (DCLS) RISC-V32 core plus an ABFT MAC — sharing one…

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ASIL-B
target
94.69%
SPFM
90.00%
LFM
FAIL
FMEDA
328K
gates
1.0.0
version
The deliverable

What you’re licensing

tilecompute is a tileable compute cluster: N compute lanes — each a dual-core-lockstep (DCLS) RISC-V32 core plus an ABFT MAC — sharing one… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

tile_compute is a tileable compute cluster: N compute lanes — each a dual-core-lockstep (DCLS) RISC-V32 core plus an ABFT MAC — sharing one ECC-protected L2 through a TL-UL fabric, with a per-tile safety island that funnels every lane fault into a single tile err_code and a defined safe state.

Key Features

Standards & Compliance

ISO 26262 ASIL-B (per-tile DCLS); scalable compute fabric

Functional Safety

ASIL-B (SEooC) · SPFM 94.69% · LFM 90.00% · FAIL

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
tile_compute #(
  .ADDR_W(6)
) u_tile_compute (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months
The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.
One vendor, one safety story
Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.
Verified, not vapor
The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Tileable RISC-V + MAC Compute Cluster?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

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Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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