Serial, Networking & Storage

AVSBus Target (PMIC-side) Device

Point-to-point AVSBus target — 8-domain voltage-setpoint link, lockstep-safe.

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ASIL-B

target

90.50%

SPFM

89.30%

LFM

PASS

FMEDA

2.1K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

AVSBus Target (PMIC-side) Device routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Point-to-point AVSBus target — 8-domain voltage-setpoint link, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable AVSBus target (PMIC/regulator-side) soft-IP — the point-to-point, controller-clocked counterpart to a PMIC’s voltage-setpoint interface.

Key Features

Point-to-point push-pull link — no open-drain pins, no clock stretching, no bus arbitration
Fixed 31-avsclk-cycle transaction: 21-bit request + 10-bit response, full-duplex-ish framing
8 independent voltage-setpoint domains, each with VSET/VOUT_RB/STATUS registers
Real fault detection: CSR-configurable global THRESH_MAX → live per-domain FAULT compare
Deferred write commit — an aborted/incomplete frame leaves NO register side effect
Diverse-DMR FSM lockstep (err_code 9)
Config + datapath register parity (err_code 1 / 2)

Standards & Compliance

AMD AVSBus v2.0/1.4.1 (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification)

Functional Safety

ASIL-B (SEooC) · SPFM 90.50% · LFM 89.30% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN
`0x04`	THRESH_MAX	RW [7:0]=global VSET fault threshold, applies to all 8 domains
`0x08`	STATUS	RO/W1C [0]=PROTO_ERR(W1C,mirrors err_code 3) [1]=TIMEOUT(W1C,mirrors err_code 4) [2]=ANY_DOMAIN_FAULT(RO, OR of all 8…
`0x0C..0x28`	VSET_RB0..7	RO [7:0] — domain N’s current VSET (host diagnostic mirror, 8 regs)

Getting Started

// Minimal instantiation
avsbus_target #(
 .ADDR_W(6)
) u_avsbus_target (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in AVSBus Target (PMIC-side) Device?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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