Serial, Networking & Storage

SMBus Slave Controller

SMBus-capable I²C slave — clock stretching, PEC, bus timeout, and ARA, lockstep-safe.

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ASIL-B

target

92.00%

SPFM

89.62%

LFM

PASS

FMEDA

1.2K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SMBus Slave Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

SMBus-capable I²C slave — clock stretching, PEC, bus timeout, and ARA, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable SMBus-capable I2C slave soft-IP — adds SMBus clock-stretching, PEC (packet error checking, CRC-8), a clock-low bus timeout, and Alert Response Address (ARA) support on top of the same core I2C slave protocol as ip/i2c_slave.

Key Features

7-bit addressable SMBus/I²C slave, configurable address register
Bounded clock stretching (bidirectional SCL) — formally proven never to hold the bus forever
PEC (CRC-8) packet-error-checking on write and read transfers
SMBus clock-low bus-timeout recovery (err_code 4)
Alert Response Address (ARA / SMBALERT#) support
Diverse-DMR FSM lockstep (err_code 9)
Config + datapath register parity (err_code 1 / 2)

Standards & Compliance

SBS SMBus Specification v3.2; NXP I²C Specification UM10204 Rev. 7

Functional Safety

ASIL-B (SEooC) · SPFM 92.00% · LFM 89.62% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN [1]=PEC_EN [2]=STRETCH_EN [3]=ALERT_REQ (HW auto-clears once an ARA cycle returns this slave’s address)
`0x04`	ADDR	RW [6:0]=7-bit slave address
`0x08`	STATUS	RO/W1C [0]=RX_READY [1]=ADDRESSED [2]=OVERRUN(W1C) [3]=RW_DIR [4]=PEC_ERR(W1C) [5]=BUS_TIMEOUT(W1C) [6]=ALERT_ACTIVE(RO)
`0x0C`	TXDATA	WO next byte to transmit on a master read (reads as 0)
`0x10`	RXDATA	RO last received byte (read clears RX_READY)

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
smbus_slave #(
 .ADDR_W(6)
) u_smbus_slave (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SMBus Slave Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space