Serial, Networking & Storage

CXPI Responder Node

LIN-derived CXPI slave node — NAD addressing, selective wake, lockstep-safe.

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ASIL-B

target

90.20%

SPFM

88.80%

LFM

PASS

FMEDA

4.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

CXPI Responder Node routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

LIN-derived CXPI slave node — NAD addressing, selective wake, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable CXPI (Clock Extension Peripheral Interface) responder node soft-IP — a LIN-derived, slave-only single-wire automotive ECU node (e.g.

Key Features

LIN-derived physical layer — BREAK+SYNC+PID(6b ID+parity)+1-8 data bytes+checksum
Static 8-bit NAD (node address) + Selective Wake frame (reserved PID, 1-byte target-NAD payload)
Auto-sleep-after-idle with 3 independent wake sources: generic wake pulse, matching-NAD Selective Wake, local WAKE_REQ
Classic/enhanced checksum selectable (CTRL.CHK_TYPE)
Diverse-DMR FSM lockstep spanning EVERY engine incl. sleep/wake control state (err_code 9)
Config + datapath register parity, incl. the RX staging buffer (err_code 1 / 2)

Standards & Compliance

JASPAR CXPI (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification); LIN 2.x physical layer

Functional Safety

ASIL-B (SEooC) · SPFM 90.20% · LFM 88.80% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN [1]=SLEEP_EN (auto-sleep-after-idle) [2]=WAKE_REQ (self-clearing command trigger) [3]=CHK_TYPE (0=classic,…
`0x04`	STATUS	RO [0]=BUSY [1]=TXDONE [2]=RXDONE [3]=ASLEEP (current sleep state) [4]=SELWAKE_SEEN (the last wake was via a matchin…
`0x08`	BAUD	RW [15:0] 16x-oversampled baud divisor (lin.sv convention)
`0x0C`	NAD	RW [7:0] this node’s own CXPI node address
`0x10`	ID	RW [5:0] the 6-bit LIN-style frame ID this node responds to

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
cxpi_node #(
 .ADDR_W(6)
) u_cxpi_node (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CXPI Responder Node?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space