Serial, Networking & Storage

ISO/IEC 7816 Contact Smart-Card ICC Controller

ISO 7816 card-side (ICC) controller — autonomous ATR, PPS negotiation, T=0 AND T=1, lockstep-safe.

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ASIL-B

target

91.05%

SPFM

89.41%

LFM

PASS

FMEDA

9.4K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

ISO 7816 card-side (ICC) controller — autonomous ATR, PPS negotiation, T=0 AND T=1, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable ISO/IEC 7816 contact smart-card ICC-side (the card itself, not the reader) controller soft-IP — a responder role, matching the catalog’s established responder/target pattern (cxpi_node/smbus_slave/pmbus_dev/avsbus_target) — this IP is the card side; a paired VIP (reader/controller side) is a later, separate effort.

Key Features

Autonomous ATR generation on RST release: TS + firmware-configured body (up to 8 bytes) + hardware-computed XOR-fold TCK
PPS negotiation (PPSS/PPS0/PPS1/PCK) — switches the active protocol (T=0↔︎T=1) and echoes Fi/Di
T=0 byte-oriented engine — full case 1/2/3/4 APDU shapes via a firmware-mediated DIR+LEN data phase + SW1SW2
T=1 block-oriented engine — I-block RX/TX with XOR-fold LRC, autonomous S(WTX) echo and bad-LRC R-block NACK
Direct/inverse convention support (CTRL.CONVENTION) + a real per-byte even-parity error-signaling pulse
Diverse-DMR lockstep spanning the 13-state card FSM, byte engines, AND protocol-select/N(S) control state (err_code 9)
Config + datapath register parity, incl. the inbound staging buffer (err_code 1 / 2)

Standards & Compliance

ISO/IEC 7816-3/-4 (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification)

Functional Safety

ASIL-B (SEooC) · SPFM 91.05% · LFM 89.41% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]EN [1]CONVENTION(0=direct,1=inverse) [2]ATR_TCK_EN [3]ERR_SIG_EN [4]RST_START(self-clearing test/diag re-ATR)
`0x04`	STATUS	RO [0]BUSY [1]ATR_DONE [2]PPS_DONE [3]CMD_RDY [4]T0_TXDONE [5]T0_RXDONE [6]T1_RXDONE [7]T1_TXDONE [8]PROTO(0=T0,1=T1…
`0x08`	BAUD	RW [15:0] 16x-oversampled etu divisor (cxpi_node.sv convention)
`0x0C`	ATR_LEN	RW [5:0] ATR bytes after TS (T0..last historical), clipped to 8

Getting Started

// Minimal instantiation
iso7816_icc #(
 .ADDR_W(6)
) u_iso7816_icc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ISO/IEC 7816 Contact Smart-Card ICC Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space