AI Inference & Acceleration

KVCE-LL — Lossless KV-Cache Codec + RD_LEVEL Dial

The bit-exact lossless tier + rate-distortion dial of the KV-cache compression family.

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ASIL-B

target

90.75%

SPFM

90.00%

LFM

PASS

FMEDA

5.9K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The bit-exact lossless tier + rate-distortion dial of the KV-cache compression family. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

kvce_ll is the lossless (RD_LEVEL 0) member of the KV-Cache Compression Engine family. Where KVCE-Lite/Std/Pro trade a bounded amount of accuracy for 2–8× capacity, KVCE-LL is a guarantee SKU: the reconstructed KV is bit-for-bit identical to the input, always.

Key Features

Bit-exact lossless KV codec (RD_LEVEL=0)
Two lossless sub-modes
RD_LEVEL rate-distortion dial
Routes lossy tiers to Lite/Std/Pro
Formal round-trip bound + ASIL-B overlay

Standards & Compliance

House KV-cache codec spec; ISO 26262 ASIL-B SEooC overlay

Functional Safety

ASIL-B (SEooC) · SPFM 90.75% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
kvce_ll #(
 .ADDR_W(6)
) u_kvce_ll (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in KVCE-LL — Lossless KV-Cache Codec + RD_LEVEL Dial?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space