Bus Bridges & Interconnect

PCIe to TileLink Bridge

TileLink wrapper for a Synopsys DesignWare PCIe controller (RC/EP) — ASIL-B.

Request this IP →Browse the catalog

ASIL-B

target

93.20%

SPFM

89.64%

LFM

PASS

FMEDA

11.8K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

TileLink wrapper for a Synopsys DesignWare PCIe controller (RC/EP) — ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

pcie_tl_bridge is a TileLink-side wrapper for a separately-licensed Synopsys DesignWare PCIe controller (DWC_pcie), presenting a PCIe root-complex or endpoint’s application interface to a TileLink SoC as an ASIL-B functional-safety element.

Key Features

Outbound SoC to PCIe + inbound PCIe-DMA to SoC via the reused TL to AXI bridges
Inbound BAR-window decode + remap with a diverse-DMR compare (err_code 9)
MSI capture to a doorbell + INTx passthrough; link-status / RAS CSRs
Config parity (err_code 1) + DW-AER / link-down (err_code 3) into safety_monitor
Config-parity + BAR-decode diagnostics formally proven (bmc + k-induction prove)

Standards & Compliance

PCIe (via a licensed DWC_pcie core), OpenTitan TileLink-UH, AMBA AXI4, ISO 26262 (SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 93.20% · LFM 89.64% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=MODE(0=RC,1=EP) [2]=MSI_EN [3]=INTX_EN

Getting Started

// Minimal instantiation
pcie_tl_bridge #(
 .ADDR_W(6)
) u_pcie_tl_bridge (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in PCIe to TileLink Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space