Alex Novickis
Principal Electronics & Systems Engineer
Remote engagements worldwide
Short version
Principal electronics and systems engineer with a multi-decade track
record across silicon, boards, firmware, and systems — from Apple’s
68K-to-PowerPC transition, through Ethernet switching silicon that
shipped over three billion dollars in product, to present-day RISC-V SoC
verification and automotive ASIL-D drive-by-wire ECUs. End-to-end:
architecture to schematic to RTL to signoff. Remote engagements
worldwide.
Long version
Apple Computer. Firmware engineer on the Macintosh
operating system, triaging and debugging code involved in the OS boot
process. Contributed to the 68K-to-PowerPC JIT compiler
that bridged Apple’s architecture transition. Later led the team that
designed end-of-line test equipment for every Apple production and
repair facility worldwide — an annual equipment budget exceeding
$220 million.
Synacom (consulting). Designed and implemented
protocol-processing engines for the encryption layer of
IS-41 / TR-54 SS7 transactions — mobile and
HLR/VLR authentication, plus cross-network roaming.
IBM / Sequent. Joined through the IBM acquisition of
Sequent Computer Systems. Chassis-controller firmware
and ASIC validation for memory systems on the
NUMA-Q architecture.
Silicon Graphics. Firmware and test-coverage
engineering for ASICs and systems.
Tektronix / Xerox. Applications engineer in the
Tektronix printer division (sold to Xerox during this
period). Supported new-product introduction in document systems — print,
fax, and scanning — with cross-functional responsibility spanning
firmware, hardware, and driver-level bug resolution from field
reports.
Intel. Wireless modelling and simulations engineer.
Ran design-of-experiments for microwave propagation channel
modelling using MATLAB, XFTD, and Wireless InSite. Directed
field experiments for 802.11 throughput and protocol simulation.
Coe Newnes-McGehee. Senior RTL architect.
Re-architected an existing RTL implementation across a 24-FPGA
Xilinx system to conform to synchronous design practices,
directing a five-designer team. Converted the flow from Leonardo
Precision to Synplicity and completed floorplanning to close timing.
Biamp. Complete product ownership across six
shipping designs. Migrated the product line from
bare-metal to Linux while holding cost and keeping the
existing plastics — end-to-end from schematic through
EMC to shipping.
Apcon. CTO and lead electronics engineer.
Shipped 38 Ethernet switching designs for
high-performance packet processing — port capacities up to 120
Tb/s, lifetime revenue over $3 billion,
products still in market. Owned silicon choice (Marvell, Broadcom,
Octeon, Fulcrum, Intel, Xpliant), signal integrity up to 25 Gbps SerDes,
DDR3/DDR4/LPDDR5X integration, custom FPGA design, RISC-V Linux kernel
driver work, and SystemC/TLA+ architectural modelling.
PolySync. Lead electronics engineer. Designed and
debugged ECUs for autonomous vehicle control using
Hercules TI safety MCUs. Safety and electrical characterization of OEM
steering, brake, and throttle subsystems. Company acquired into Vay.
Vay. Principal electronics engineer. Architected and
implemented drive-by-wire automotive ECUs on Infineon
TriCore for autonomous vehicle control. Designed an ADAS system
on TI TDA4VH Jacinto with MIPI/APHY/GMSL camera feeds, PCIe 3,
DDR4. Authored FTA, FMEA, and FMEDA documentation in compliance
with ISO 26262 for ASIL-D safety goals. Ran PCB thermal aging
and vibration studies in Ansys and Sherlock.
Earlier consulting and contract work. Significant
projects across instrumentation, life sciences, medical, marine, and
entertainment hardware: – Molecular Dynamics / Amersham / GE
Healthcare — DNA electrophoresis scanner and image-processing
pipeline. – Luminex — X-ray and high-resolution
greyscale video card with on-board feature extraction for medical
imaging. – Welch Allyn — vitals-monitor consulting
(medical-grade patient monitoring). – Intel — secure media
delivery — additional Intel engagement on protected media
delivery over secure channels (separate from the wireless propagation
work above). – Personal submersible watercraft —
single-occupant scuba propulsion craft. Designed the electronics package
and full salt-water waterproofing stack — sealing, materials, corrosion
control, and depth-rated wet/dry barriers. – Console-game
development hardware — SEGA / NES development system for a
Menlo Park studio (early-1990s era).
Consulting (ongoing). Present work spans ASIC
front-end (RTL, SystemVerilog, VCS/Xcelium), real-time OS kernel
development, IP integration (LPDDR5, 32G SerDes, Ethernet
MAC/PHY/Switch), ZeBu/HAPS emulation, and architectural performance
modelling with GEM5. Current focus: AI inference
silicon — adapting the CTX storage, L1–L3 cache hierarchy, and
memory subsystem to the access patterns of transformer workloads with
compressed KV cache.
Tools & platforms (partial
list)
Silicon & Verification: RISC-V · custom SoC ·
SystemVerilog · UVM · SystemC · Chisel · Synopsys VCS · Verdi · DC ·
Formality · Cadence Xcelium · Forte · Spectre · Spice · JasperGold ·
TLA+
Emulation & Prototyping: Synopsys ZeBu ·
Synopsys HAPS · Xilinx Vivado · Altera Quartus · Lattice Diamond ·
Synplicity
High-speed & Memory: PCIe Gen2–5 · Ethernet
1G–400G · SGMII · RGMII · XGMII · XLAUI · USB 3.0 · MIPI · DDR3 · DDR4 ·
LPDDR5X (DFI interface, training algorithms) · SerDes
1G–25G
Safety & Automotive: ISO 26262 ASIL-A through
ASIL-D · IEC 61508 · FMEDA · FMEA · FTA · AUTOSAR · Infineon TriCore
399XX · TI TDA4VH Jacinto · Hercules TI safety MCU · CAN
Signal & Power Integrity: Altium · Cadence
Allegro · OrCAD · HyperLynx · SiWave · Ansys Sherlock · Sigrity
(TopSpeed) · IBIS · LTspice · 2.5D FEA
Firmware & Software: U-Boot · Linux kernel
(RISC-V, ARM, PowerPC, MIPS) · bare-metal · RTOS · GEM5
Languages: C · C++ · Rust · Python · SystemVerilog ·
Verilog · VHDL · SystemC · Assembly (ARM, RISC-V, 68K, x86) · Java ·
JavaScript / Node.js · .NET · Tcl · Bash · SQL · awk · Perl
Selected achievements
- 38 Ethernet switching designs delivered at Apcon,
>$3 B lifetime revenue - ASIL-D certification for production drive-by-wire
ECUs at Vay - $220 M annual test-equipment budget managed at
Apple - JIT compiler contribution for the 68K-to-PowerPC
architectural transition - 64-core RISC-V SoC pre- and post-silicon validation
with LPDDR5X, 100G Ethernet, PCIe Gen2–5 - AI inference chip design with compressed KV-cache
architecture for transformer workloads — actively adapting CTX
storage, L1–L3 cache hierarchy, and memory subsystem for
inference performance
Credentials
- IPC CID — Certified Interconnect Designer
- IPC CID+ — Certified Interconnect Designer,
advanced level - 6+ years of active PCB-layout practice in the CID /
CID+ field - 25+ years of circuit-board design across analog,
digital, and mixed-signal - Signal & power integrity — channel modeling ·
PDN (power delivery network) validation · IR-drop loss analysis ·
pre-layout constraint development · IBIS / 2.5D FEA · post-layout
extraction and correlation
Languages
- English — native
- Russian — fluent
- Spanish, German — beginner
Outside engineering
Independent research in theoretical physics — topological soliton
models with implications for particle physics and cosmology. Published
on Zenodo
and GitHub.
Keeps first-principles thinking sharp, which turns out to be useful for
architecture work too.