Free tool

Op-Amp Error Budget Calculator

Enter the amplifier's specifications and your converter. Every error term is referred to the input where they are comparable, ranked by size, and expressed in LSBs of the ADC you are actually feeding — so you can see which single specification is costing you resolution.

Noise gain — V/V, 1 + Rf/Rg

Full-scale output swing — V

ADC resolution — bits

Source / balance impedance — kΩ

Temperature span from calibration — °C

Noise bandwidth — kHz

Input offset V_OS— µV

V_OS drift — µV/°C

Input bias current I_B— nA

Input offset current I_OS— nA

CMRR / PSRR — dB, and supply variation in V

Voltage noise density — nV/√Hz

Open-loop gain A_OL— dB

1 LSB

–

Total error, RSS

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Total error, worst case

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Usable resolution

–

bits, error-limited

Error term	Referred to input	At the output	LSBs	Share

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Why the datasheet's headline number is the wrong one

Amplifier selection usually starts with a specification that turns out not to matter. A part with 25 µV of offset looks obviously better than one with 150 µV — until you notice the circuit is calibrated at final test, which removes offset entirely, and that what survives calibration is drift. Meanwhile the bias current flowing through a 10 kΩ source can be contributing more error than either.

The only way to see this is to put every term in the same units and rank them. That is all this tool does: each specification is referred to the input, where they are directly comparable, then multiplied by the noise gain to reach the output and divided by an LSB so the number means something in the converter you are actually feeding.

Reading the table

Offset is trimmable; drift is not. If the product is calibrated, strike the offset row mentally and look at drift over your real temperature span. If it is not calibrated, offset usually dominates everything and the argument is over.
Bias current only matters through impedance. I_B times the source resistance is a voltage, and it grows with the source. This is why a FET-input amplifier is transformative on a megohm sensor and irrelevant on a 100 Ω one. If both inputs see matched impedance the bias term largely cancels and what remains is the offset current, which is why the two are listed separately.
CMRR is zero in a true inverting stage because the input node does not move. It bites hardest in a non-inverting buffer swinging rail to rail.
PSRR turns supply ripple into signal error. If the amplifier runs from a switcher, the relevant supply variation is not the DC tolerance, it is the ripple — and PSRR degrades with frequency, often badly, so the DC figure on the front page is optimistic.
Finite open-loop gain sets a floor on gain accuracy. At a noise gain of 100 and 110 dB of A_OL you have roughly 0.03% of gain error before any resistor tolerance is considered.

RSS or worst case

Both are shown because they answer different questions. The worst-case sum assumes every error is simultaneously at its limit and in the same direction — correct for a guaranteed-by-design argument, and what a safety case needs. RSS treats them as independent random variables and is much closer to what a production population actually looks like, but it guarantees nothing about an individual unit.

The gap between them is often a factor of two. Quoting RSS where worst case was required is one of the more common ways an error budget passes review and then fails in the field.

Noise is included as an RMS figure, which is not the same kind of number as the others. If you need a peak-to-peak error for a threshold or a comparator, multiply the noise term by about 6 for a 3-sigma estimate before adding it to the DC terms.

What this does not model

1/f noise below the flatband corner, which for a chopper is negligible and for a plain bipolar part can dominate a slow measurement. The signal-chain noise budget handles noise properly.
Gain-setting resistor tolerance and drift, which for a discrete network is frequently larger than the amplifier's own contribution. The divider calculator covers that side.
Settling, slew and bandwidth — this is a DC and low-frequency budget. A stage that is accurate but has not settled is still wrong when the ADC samples it.
Input common-mode and output swing limits, which are hard constraints rather than error terms and will simply clip.

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