ISO 26262 · RISC-V · Functional-Safety Soft-IP

You’re not buying RTL.
You’re skipping the certification schedule.

Synthesizable, portable SystemVerilog soft-IP that ships with the functional-safety work already done — per-IP FMEDA, safety manual, IP-XACT, and a bit-exact testbench in the box.

Talk to us →Explore the catalog
Why engineering leaders engage us

The 12–18 months you don’t have to spend

The value isn’t the code — vendors will sell you RTL. It’s the safety case that normally takes a dedicated team a year and a half to assemble. We ship it with the IP.

Same ASIL-ready safety case — a fraction of the scheduleBuild in-houseLicense our IPSpecDesignFMEDAVerifySign-off≈ 12–18 months you skipASIL-ready safety case ✓✓ same safety case, in weeks0369121518months
176
IP blocks
verified, ASIL-B SEooC
ASIL-D
island roll-up
on measured coverage
99.42%
SPFM
safety-island FMEDA
bit-exact
PQC crypto
vs NIST reference
in the box
FMEDA + manual
per IP, day one
Subsystems & catalog

What we ship

RISC-V Safety Island →

Dual-core lockstep compute + secure boot + freedom-from-interference + a graded fault hub.

ASIL-D roll-up

Functional-Safety NPU Island →

All-digital ASIL NPU with a SOTIF output-plausibility monitor on the result itself.

safety-wrapped

CHI Coherent-Memory Fabric →

AMBA-5 CHI coherency onto a real LPDDR5 controller, ordering proven by formal.

formally proven

Post-Quantum Crypto →

ML-KEM & ML-DSA (FIPS 203/204) accelerators, every primitive checked bit-exact.

NIST-aligned

Safety Mechanisms →

ECC/SECDED memory, 2-of-3 TMR voters, lockstep safety wrappers, LBIST, watchdogs, and a fault-collection unit.

23 blocks

Automotive & Networking →

CAN 2.0 / FD / XL, FlexRay, automotive Ethernet, I²C / I³C, UART, SPI — field-proven serial links.

25 blocks

Aerospace & Space →

MIL-STD-1553, ARINC 429 / 629 / 664 / 717 / 818 / 825, and CCSDS space links.

15 blocks

The full 176-IP Catalog →

Search or filter the entire library — each block with its own FMEDA, safety manual, and testbench.

browse all IP
Proof, not adjectives

Real silicon flow — not slideware

Every claim traces to an artifact you can inspect under NDA: synthesized area, routed layout on a real PDK, fault-injection waveforms, and failure-rate-weighted FMEDA roll-ups.

RISC-V Safety Island — block diagram
RISC-V Safety Island — block diagram
Subsystem FMEDA roll-up (SPFM / LFM / PMHF)
Subsystem FMEDA roll-up (SPFM / LFM / PMHF)
Dual-core lockstep comparator waveform
Dual-core lockstep comparator waveform
Mixed-signal PLL/CDR macro — routed on a real PDK
Mixed-signal PLL/CDR macro — routed on a real PDK
Digital block — routed on a real PDK
Digital block — routed on a real PDK
Graded fault-collection unit reaction
Graded fault-collection unit reaction
For the people who own the risk

Why it’s different

Safety work products in the box
FMEDA, safety manual, IP-XACT, and a bit-exact testbench ship with every IP — not a datasheet promising them later.
Engineered as ASIL-B SEooC
A Safety Element out of Context baseline across the catalog; the Safety Island roll-up lands at ASIL-D on measured diagnostic coverage.
Verified, not vapor
Every listing is backed by RTL that builds and passes (make ); crypto is checked bit-exact against the reference implementations.
Portable RTL
Vendor-neutral SystemVerilog that maps cleanly onto your existing SoC fabric — no foundry or tool lock-in.

How engagement works

1
Talk to us
Tell us the block or subsystem and your target ASIL.
2
Mutual NDA
We open the data room: full FMEDA, DFA, RTL, and pricing.
3
Evaluate
Review the work products and integrate against a time-boxed eval.
4
License
Take the RTL + safety case into your program.

Who it’s for

Automotive, industrial, robotics, and aerospace SoC teams moving to RISC-V and needing a defensible functional-safety story — without standing up a safety-IP group from scratch.

Have a subsystem in mind?

Engagements start with a conversation and a mutual NDA. Pricing and the full FMEDA / DFA / RTL data room follow.

Talk to us →Browse the IP catalog

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. “ISO 26262-ready” means the work products are generated — not that the IP is third-party certified.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space