Cryptography & Data Integrity

AES Cipher Engine

A multi-mode AES-128/192/256 block cipher accelerator delivered as synthesizable SystemVerilog,

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ASIL-B

target

100.00%

SPFM

90.00%

LFM

PASS

FMEDA

49.4K

gates

11.0.0

version

The deliverable

What you’re licensing

A multi-mode AES-128/192/256 block cipher accelerator delivered as synthesizable SystemVerilog, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A multi-mode AES-128/192/256 block cipher accelerator delivered as synthesizable SystemVerilog, implementing the FIPS-197 forward and inverse cipher across eight operating modes (ECB, CTR, CBC, OFB, CFB, XTS, GCM/GHASH, CMAC) behind a single APB4 slave register interface.

Key Features

AES-128/192/256 (10/12/14 rounds) selected at START via CTRL[13]=KEY192 or CTRL[5]=KEY256; on-the-fly key expansion for AES-128, a word-serial stored-schedule pre-pass for AES-192, and a sliding-window schedule for AES-256
Eight operating modes in one core — ECB, CTR (auto-incrementing counter), CBC (auto-chaining IV), OFB, CFB, XTS (tweak storage), the GHASH primitive, and full GCM authenticated encryption/decryption with a hardware AAD-handling FSM (NIST SP 800-38D)
CMAC subkey derivation (K1/K2 via CTRL[7]=CMAC_SUBKEY) and last-block automation (CTRL[8]/[9]) per NIST SP 800-38B
One round per clock; a 128-bit block completes in ≈11 cycles (AES-128 encrypt) to ≈27 cycles (AES-256 decrypt); a maskable DONE interrupt (aes_irq) signals completion
Dual-rail cipher datapath — state, key schedule (incl. the AES-192/256 stored schedules), and the GCM GHASH accumulator + tag-compare all run on two independent rails, compared every round → err_code 9, so a corrupted comparator cannot wrongly pass a forged GCM tag
Per-word even parity on every key/operand register (KEY0..7, IN, PT, K1, K2, GCM H / E(K,J0) / received-tag) → err_code 1
Key and GCM-secret registers are write-only in effect: the register map allows RW, but read-back returns 0x0 for KEY0..7 / IN0..3 / the GCM secret operands — key material cannot be exfiltrated over the same APB port that loaded it

Standards & Compliance

FIPS-197 (AES); NIST SP 800-38A (CBC/CFB/OFB/CTR), 800-38B (CMAC), 800-38D (GCM), 800-38E (XTS); ISO 26262-5 ASIL B (SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=START [1]=DECRYPT [2]=CTR_MODE [3]=GHASH [4]=GHASH_INIT [5]=KEY256 (1 -> AES-256, 14 rounds) [6]=CBC_MODE (PT reg…
`0x04`	STATUS	RO [0]=BUSY [1]=DONE
`0x08..0x14`	KEY0..3	(low half of the key; the only key for AES-128)
`0x18..0x24`	IN0..3	(ECB: plaintext/ciphertext. CTR: counter block. HW post-increments LSB.)
`0x28..0x34`	OUT0..3	(RO result: ECB ciphertext/plaintext; CTR = AES(counter) XOR PT)

…5 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
aes #(
  .ADDR_W(6)
) u_aes (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in AES Cipher Engine?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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