System, Safety & Compute

INT8 Systolic GEMM MAC Array

A hardware multiply-accumulate engine for neural-network inference, delivered as synthesizable soft-IP.

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ASIL-B

target

92.55%

SPFM

90.00%

LFM

PASS

FMEDA

28.6K

gates

0.1.0

version

The deliverable

What you’re licensing

A hardware multiply-accumulate engine for neural-network inference, delivered as synthesizable soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A hardware multiply-accumulate engine for neural-network inference, delivered as synthesizable soft-IP. NN layers (convolutions, fully-connected) reduce to matrix multiplies (GEMM); this IP does that GEMM in a SIZE×SIZEsystolic array of INT8 multiply-accumulate processing elements — the same dataflow as a small TPU or the AURIX TC4xx PPU.

Key Features

Output-stationary SIZE×SIZE systolic PE array (parameterizable)
Signed INT8 → INT32 accumulation
ABFT column-checksum fault detection (err_code 2)
A/W operand-buffer per-entry parity (err_code 1)
Streaming-control diverse-DMR lockstep (err_code 9)
SPFM 90.75% ASIL-B PASS

Standards & Compliance

INT8 quantization per TFLite / ONNX Runtime (integer arithmetic)

Functional Safety

ASIL-B (SEooC) · SPFM 92.55% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=START(self-clear)
`0x04`	STATUS	[0]=BUSY [1]=DONE
`0x40`	AROW0	activation row 0 (4x INT8)
`0x44`	AROW1	activation row 1 (4x INT8)
`0x48`	AROW2	activation row 2 (4x INT8)

…21 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
ai_mac #(
  .ADDR_W(6)
) u_ai_mac (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in INT8 Systolic GEMM MAC Array?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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