Avionics, Space & Mil-Std Networking

ARINC 429 Avionics-Bus Transmitter/Receiver

ARINC 429 avionics-databus transmitter/receiver with label filtering and dual-FIFO word framing, ASIL-B / DO-254-ready.

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ASIL-B

target

92.43%

SPFM

99.00%

LFM

PASS

FMEDA

4.2K

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

ARINC 429 Avionics-Bus Transmitter/Receiver routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

ARINC 429 avionics-databus transmitter/receiver with label filtering and dual-FIFO word framing, ASIL-B / DO-254-ready. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

ARINC 429 avionics-databus transmitter/receiver with an APB4 slave interface and a rad-tolerant / ASIL-B safety monitor.

Key Features

Hardware ARINC 429 word framing: LABEL[8]/SDI[2]/DATA[19]/SSM[2]/odd-PARITY[1] assembled and parsed in the TX_LOAD/RX_CHECK states, with dual bit-rate support (12.5 kbps / 100 kbps via CFG.HI_SPEED)
8-deep TX word FIFO and 8-deep SECDED-protected RX word FIFO (fifo_ecc) decouple the APB4 register plane from bit-serial wire timing; a double-bit RX FIFO fault reports err_code 2
8-entry RX label accept-list (LBL_FILT) filters unwanted labels in hardware before software ever sees them; off-list labels with good parity are silently dropped as normal operation
External BPRZ line-driver/receiver boundary at tx_bit/tx_bit_en and rx_bit/rx_bit_en — the analog bipolar line signalling is entirely off-chip, so any HI-8585/DEI1082-class transceiver can be wrapped in
CTRL.LOOPBACK self-test folds the TX serial bit into the RX deserializer, exercising serialize-parity-deserialize-check-filter-store end to end without an external bus
Complementary-DMR lockstep across the TX and RX serdes FSMs (err_code 9) plus config-register even parity (err_code 1) and RX word odd-parity/framing detection (err_code 3), all latched by the shared safety_monitor
APB4 register map (4-byte stride): CTRL 0x00, STATUS 0x04, CFG 0x08, TX_DATA 0x0C, RX_DATA 0x10, LBL_FILT 0x14, IER 0x18, ISR 0x1C (W1C), ERR 0x20 (W1C)

Standards & Compliance

ARINC 429 (Mark 33 DITS); DO-254/ED-80 airborne electronic hardware design-assurance framing; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 92.43% · LFM 99.00% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the RTCA DO-254 assurance case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 CFG 0x0C TX_DATA 0x10 RX_DATA
`0x14`	LBL_FILT	0x18 IER 0x1C ISR(W1C) 0x20 ERR(W1C) [8:6]tx_state [11:9]rx_state [15:12]rxfifo level [19:16]txfifo level

Getting Started

// Minimal instantiation
arinc429 #(
 .ADDR_W(6)
) u_arinc429 (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ARINC 429 Avionics-Bus Transmitter/Receiver?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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