AXI4-to-TileLink-UH Bridge

What it is

axi4_to_tl_uh is a synthesizable SystemVerilog bridge that terminates a full AXI4 slave port — INCR bursts, single-outstanding — and re-issues each accepted beat as one TileLink-UH A-channel request (TL_GET for reads, TL_PUT_FULL/TL_PUT_PARTIAL for writes), returning the D-channel response on AXI R/B, with built-in ASIL B safety instrumentation.

Key Features

• Full AXI4 slave port: INCR bursts (arlen/awlen up to 256 beats), single-outstanding — one in-flight TL-A request at a time, tl_a_source fixed to 0
• One TL-UH A-channel request per AXI beat: TL_GET for reads, TL_PUT_FULL/TL_PUT_PARTIAL for writes selected by whether wstrb is all-ones
• Error/response mapping: TL-D denied/corrupt or an unexpected D-channel opcode sticky-latches and reports as AXI RRESP/BRESP = SLVERR (err_code 5/6)
• Per-transaction watchdog (TIMEOUT_CYCLES, default 256) bounds a hung TL fabric and forces a synthesized SLVERR (err_code 4)
• ASIL-B config parity on the captured AXI ID/address (err_code 1) and true 64-bit full-word SECDED on both data-beat buffers, single-bit auto-correct / double-bit detect (err_code 2)
• Complementary-redundant FSM lockstep shadow across the 8-state sequencer, formally proven fault-free (err_code 9)
• Single clock domain (clk/rst_n) shared by both interfaces — no internal CDC; catalog FMEDA: SPFM 91.80%, LFM 89.35%, PMHF 4.40×10⁻⁹/h, PASS ASIL-B

Standards & Compliance

AMBA AXI4 (slave, INCR bursts); TileLink-UH (master, A/D channels); ISO 26262 ASIL-B SEooC (SPFM 91.80%, LFM 89.35%, PMHF 4.40×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.80% · LFM 89.35% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
axi4_to_tl_uh #(
  .ADDR_W(6)
) u_axi4_to_tl_uh (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.