AXI4-Lite to TL-UL Bridge

What it is

A single-outstanding protocol bridge that translates AMBA AXI4-Lite subordinate transactions (AR/R reads, AW+W/B writes) into TileLink Uncached Lightweight (TL-UL) GET / PUT_FULL / PUT_PARTIAL requests, delivered as synthesizable SystemVerilog with a full ASIL B safety layer.

Key Features

• Translates AXI4-Lite AR/R reads and AW+W/B writes into TL-UL GET (opcode 4), PUT_FULL (opcode 0, all-ones strobe), or PUT_PARTIAL (opcode 1) — single-outstanding, one transaction end-to-end through a 6-state FSM (IDLE→WAIT_W/WAIT_AW→ISSUE→WAIT_TL_D→RESPOND)
• Single clock domain, verified no internal CDC — one clk drives every register on both the AXI4-Lite and TL-UL sides; crossing clock domains requires an external CDC element outside the bridge
• SECDED (G-9, 7-check-bit Hamming, ecc_pkg) on both the write-data and read-data buffers, corrected in-line before driving tl_a_data/axil_rdata; a double-bit error raises err_code 2
• Even parity over the latched request address (addr_par_q); a mismatch outside IDLE raises err_code 1
• Diverse-DMR complementary-redundant FSM shadow (state_cmpl_q, an independent next-state cone that never reads state_q) catches control-logic divergence as err_code 9 (ASIL-D-leaning mechanism)
• Configurable timeout_monitor (TIMEOUT_CYCLES) synthesizes an AXI SLVERR if the TL-UL fabric stalls in ISSUE/WAIT_TL_D (err_code 4); tl_d_denied/tl_d_corrupt fold into the same SLVERR — the bridge never generates DECERR since it performs no address decoding
• SPFM 91.80%, LFM 89.35%, PMHF 2.56×10⁻⁹/h — ASIL-B PASS (pre-sign-off engineering FMEDA); SVA protocol assertions verify valid/ready stability in simulation

Standards & Compliance

AMBA AXI4-Lite (subordinate side); TileLink Uncached Lightweight, TL-UL (manager side); ISO 26262 ASIL-B SEooC (SPFM 91.80%, LFM 89.35%, PMHF 2.56×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.80% · LFM 89.35% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
axi4lite_to_tl_ul #(
  .ADDR_W(6)
) u_axi4lite_to_tl_ul (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.