Bus Bridges & Interconnect

AXI4-Stream Bridge

axi4sbridge bridges a TileLink-UL (memory-mapped) control plane to an AXI4-Stream data plane: software pushes/pops TVALID/TREADY/TDATA/TKEEP/…

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ASIL-B

target

92.70%

SPFM

89.08%

LFM

PASS

FMEDA

2.2K

gates

1.0.0

version

The deliverable

What you’re licensing

axi4sbridge bridges a TileLink-UL (memory-mapped) control plane to an AXI4-Stream data plane: software pushes/pops TVALID/TREADY/TDATA/TKEEP/… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

axi4s_bridge bridges a TileLink-UL (memory-mapped) control plane to an AXI4-Stream data plane: software pushes/pops TVALID/TREADY/TDATA/TKEEP/ TLAST/TUSER stream beats through a small register window.

Key Features

TL-UL slave register window: TXDATA (0x00, push), TXCTRL (0x04, latches TLAST/TKEEP/TUSER for the next push), RXDATA (0x08, pop), STATUS (0x0C, {rx_last,rx_valid,tx_full,tx_empty,rx_full,rx_empty}) — single-outstanding IDLE→EXEC→RESPOND FSM
AXI4-Stream master TX (drains the TX FIFO, m_axis_tvalid=!tx_empty) and AXI4-Stream slave RX (fills the RX FIFO, s_axis_tready=!rx_full) side by side, one clock domain, no width conversion — pair with width_cdc_bridge for a cross-clock or width-mismatched peer
Dual-lane fifo_ecc SECDED per direction (32-bit TDATA + packed TUSER/TLAST/TKEEP sideband) sharing one write/read enable so the two lanes’ pointers never skew; any double-bit error → err_code 2
Backpressure surfaced, not swallowed: a TXDATA push to a full TX FIFO or an RXDATA pop from an empty RX FIFO returns tl_d_denied (plus tl_d_corrupt on the read) instead of a silent drop
Config/address/source register parity recomputed every non-IDLE cycle → err_code 1; an unsupported TL-UL opcode accepted at IDLE → err_code 3 protocol guard
Complementary-redundant shadow FSM (state_cmpl_q, an independent next-state cone) — any lockstep divergence → err_code 9 — all codes funnelled to a shared safety_monitor with err_clear/err_valid/err_code[3:0]
ASIL-B SEooC: SPFM 92.70%, LFM 89.08%, PMHF 3.02×10⁻⁹/h (PASS); FIFO_DEPTH, DATA_W, SOURCE_W, USER_W all parameterizable

Standards & Compliance

AMBA AXI4-Stream protocol (TVALID/TREADY/TDATA/TKEEP/TLAST/TUSER); TileLink-UL memory-mapped control plane; ISO 26262 ASIL-B SEooC (SPFM 92.70%, LFM 89.08%, PMHF 3.02×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.70% · LFM 89.08% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	TXDATA	(W) push TDATA word into TX FIFO (consumed by AXIS master)
`0x04`	TXCTRL	(W) [0]=TLAST for the next pushed word, [8+:KEEP_W]=TKEEP, [(8+KEEP_W)+:USER_W]=TUSER
`0x08`	RXDATA	(R) pop one beat from RX FIFO -> TDATA in [DATA_W-1:0]
`0x0C`	STATUS	(R) {rx_last, rx_valid, tx_full, tx_empty, rx_full, rx_empty}

Getting Started

// Minimal instantiation
axi4s_bridge #(
  .ADDR_W(6)
) u_axi4s_bridge (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in AXI4-Stream Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

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Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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