RISC-V Cores & SoC Platform

SECDED Cache Controller

cachectrl is an ASIL-B set-associative write-back cache controller with SECDED protection, delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

96.03%

SPFM

88.31%

LFM

PASS

FMEDA

38.0K

gates

1.0.0

version

The deliverable

What you’re licensing

cachectrl is an ASIL-B set-associative write-back cache controller with SECDED protection, delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

cache_ctrl is an ASIL-B set-associative write-back cache controller with SECDED protection, delivered as synthesizable SystemVerilog soft-IP.

Key Features

Set-associative write-back + pseudo-LRU
SECDED tag + data arrays (\rightarrow) DBE err_code 2
Fill/writeback timeout (err_code 4)
Cache-control FSM DMR (err_code 9)
Tag/state plausibility (err_code 3) + config parity (err_code 1)
For application cores (safety core uses TCM)

Standards & Compliance

ISO 26262 (SEooC)

Functional Safety

ASIL-B (SEooC) · SPFM 96.03% · LFM 88.31% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN cache enable [1]=FLUSH (write 1 -> flush+invalidate all) [2]=INVAL (write 1 -> invalidate all, no writeback)
`0x04`	STATUS	[0]=BUSY (flush in progress) [1]=err_valid [5:2]=err_code
`0x08`	HITCNT	hit counter (RO)
`0x0C`	MISSCNT	miss counter (RO)
`0x10`	SBECNT	SECDED single-bit-corrected counter (RO)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
cache_ctrl #(
  .ADDR_W(6)
) u_cache_ctrl (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SECDED Cache Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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