Serial, Networking & Storage

CAN-XL Tri-Mode Bus Controller

A configurable CAN classic + CAN-FD + CAN-XL tri-mode bus controller delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

95.52%

SPFM

90.00%

LFM

PASS

FMEDA

42.0K

gates

1.0.0

version

The deliverable

What you’re licensing

A configurable CAN classic + CAN-FD + CAN-XL tri-mode bus controller delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable CAN classic + CAN-FD + CAN-XL tri-mode bus controller delivered as synthesizable SystemVerilog soft-IP.

Key Features

Tri-mode frame engine — Classic CAN 2.0B (8 B, CRC-15), CAN-FD (64 B, CRC-17/21), and CAN-XL (up to 2048 B, CRC-24) selected by the FDF/RES/XLF header bits on one shared 28-state bit-serial FSM
CAN-XL header fields: 8-bit VCID (256 filterable virtual networks via VCID_FILT), 8-bit SDT service-data-type, 3-bit PRIO, and a full 32-bit Acceptance Field (TXAF/RXAF) carried MSB-first under CRC-24
Three independent bit-timing domains — BTR (arbitration), FDBTTR (FD data phase), XLBTTR (XL data phase) — each with its own PRESC/TSEG1/TSEG2/SJW so classic, FD, and XL segments of one frame run at their own rate
2048-byte RX FIFO with per-32-bit-lane SECDED (512 lanes × 7 check bits) plus SECDED-protected id/ctrl/VCID-SDT/DL/AF metadata FIFOs — single-bit corrected in-line, double-bit → err_code 2
Even-parity-checked CR/BTR/XLBTTR config registers → err_code 1; hardware TEC/REC fault confinement (EWRN≥96, EPAS≥128, BOFF at TEC≥256) → err_code 3
Complementary-redundant diverse-DMR FSM lockstep shadow spanning the shared TX/RX bit engine (arbitration, header, CRC, bit-stuffing) → err_code 9, aggregated with every mechanism above into one safety_monitor (err_valid/err_code[3:0])
Hardware loopback (CR.LOOPBACK) for bring-up self-test of the digital bit engine, independent of the external CiA 610-3 transceiver and the physical bus

Standards & Compliance

CiA 610-1 / ISO 11898-1:2024 (CAN-XL); ISO 11898-1:2015 (CAN-FD) and CAN 2.0B backward-compatible; CiA 610-3 / ISO 11898-2:2024 Amendment 1 (XL PHY, external transceiver); ISO 26262 ASIL-B SEooC (SPFM 95.52%, LFM 90.00%, PMHF 3.54×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 95.52% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x000`	CR	[7]=EN [6]=LOOPBACK [5]=FD_EN [4]=XL_EN [1]=TXEIE [0]=RXNEIE
`0x004`	SR	[5]=BOFF [4]=EPAS [3]=EWRN [2]=BSY [1]=RXNE [0]=TXRDY
`0x008`	ESR	[15:8]=TEC [7:0]=REC
`0x00C`	BTR	[28:24]=SJW [23:16]=TSEG2 [15:8]=TSEG1 [7:0]=PRESC
`0x010`	FDBTTR	[23:16]=TSEG2FD [15:8]=TSEG1FD [7:0]=PRESCFD

…6 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
can_xl #(
  .ADDR_W(6)
) u_can_xl (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CAN-XL Tri-Mode Bus Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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