CHI Interconnect & Coherency

CHI Home Node

chihnf is a synthesizable SystemVerilog CHI Home Node (HN-F): the point-of-coherency and point-of-serialization for a snoopable address region of an…

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ASIL-B

target

90.75%

SPFM

89.71%

LFM

PASS

FMEDA

12.5K

gates

0.2.0

version

The deliverable

What you’re licensing

chihnf is a synthesizable SystemVerilog CHI Home Node (HN-F): the point-of-coherency and point-of-serialization for a snoopable address region of an… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

chi_hn_f is a synthesizable SystemVerilog CHI Home Node (HN-F): the point-of-coherency and point-of-serialization for a snoopable address region of an AMBA 5 CHI (Issue E) interconnect, with built-in ASIL-B safety instrumentation.

Key Features

Point-of-coherency + point-of-serialization: fully-associative directory (DIR_ENTRIES lines, sharer vectors, even parity) drives every snoop/allocate/evict decision
ReadShared adds a sharer (downgrading a unique owner via SnpShared first); ReadUnique runs a multi-snoop SnpUnique invalidate loop against every other sharer
Directory eviction with back-invalidation: a miss into a full directory SnpUnique-invalidates the round-robin victim’s sharers before reuse
Dirty SnpRespData forwarded as the line, else sourced from the single-outstanding SN-F memory port (mem_req/we/addr/wdata/be)
SN-F read error (mem_rerr) surfaced as a fault AND propagated as a CHI RespErr (DataError) on CompData/Comp — never silently dropped (err_code 3)
Single-outstanding by design: config/address parity (err_code 1), line-buffer SECDED + directory parity (err_code 2), outstanding-transaction watchdog (err_code 4), command-FSM diverse-DMR shadow (err_code 9)
Catalog FMEDA: SPFM 90.75%, LFM 89.71%, PMHF 2.32×10⁻⁸/h, PASS ASIL-B; formal bmc (DMR-clean, one-hot) + cover (CompData/Comp/snoop reachable)

Standards & Compliance

Arm AMBA 5 CHI (Issue E); ISO 26262 ASIL-B SEooC (SPFM 90.75%, LFM 89.71%, PMHF 2.32×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.75% · LFM 89.71% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (accept requests) [1]=SNOOP_EN (coherent snooping)
`0x04`	SNP_BASE	RW snoopable region base (byte address, low 4 GiB)
`0x08`	SNP_LIMIT	RW snoopable region limit (exclusive)
`0x0C`	STATUS	RO [9:0]=FSM state [13:10]=err_code [14]=err_valid

Getting Started

// Minimal instantiation
chi_hn_f #(
  .ADDR_W(6)
) u_chi_hn_f (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CHI Home Node?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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