The deliverable
What you’re licensing
N\TXN-deep coherent-read pipeline (default 2): independent O\SNOOP → O\SNPW → O\MEMRD → O\CDATA slots let up to N\TXN ReadShared/ReadUnique snoops be… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.
Key Features
- N_TXN-deep coherent-read pipeline (default 2): independent O_SNOOP → O_SNPW → O_MEMRD → O_CDATA slots let up to N_TXN ReadShared/ReadUnique snoops be outstanding at once
- Per-line hazard-stall: a request whose address matches any non-free slot is refused a credit (chi_rxreq_lcrdv held low) until that slot frees — correct-by-construction serialization, formally proven (a_hazard, bmc) and non-vacuously covered (c_2active)
- Single-owner directory (DIR_ENTRIES lines, {valid,tag,owner}): ReadShared and ReadUnique both SnpUnique-invalidate a different current owner and hand the requester sole ownership — no multi-sharer tracking in this tier
- Tagged SN-F memory port (mem_txnid/mem_rtxnid) and slot-tagged snoop routing (chi_txsnp_txnid = slot number) — a compliant adapter may return reads out of issue order; lowest-active-slot-first arbitration for the shared TXSNP/mem-read/TXDAT resources
- Per-slot held-line inline SECDED (ecc_pkg 64-bit words): a single-bit upset in a slot’s buffered line is corrected before CompData is driven, a double-bit is flagged uncorrectable (err_code 2)
- Stricter opcode admission than v2: only ReadNoSnp/ReadShared/ReadUnique/WriteNoSnp are ever granted a credit — an unrecognized opcode is simply never accepted, rather than v2’s silent plain-read fall-through
- ASIL-B: config/address parity (err_code 1), per-slot held-line SECDED (err_code 2), SN-F read-error + RespErr propagation (err_code 3), outstanding-transaction watchdog covering slots and the write FSM (err_code 4), write-FSM complementary diverse-DMR shadow (err_code 9); catalog FMEDA SPFM 90.81%, LFM 89.38%, PMHF 1.67×10⁻⁸/h, PASS ASIL-B
Standards & Compliance
Arm AMBA 5 CHI (Issue E); ISO 26262 ASIL-B SEooC (SPFM 90.81%, LFM 89.38%, PMHF 1.67×10⁻⁸/h)
Functional Safety
ASIL-B (SEooC) · SPFM 90.81% · LFM 89.38% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
| Offset | Register | Description |
|---|
0x00 | CTRL | RW [0]=EN (accept requests) [1]=SNOOP_EN (coherent snooping) |
0x04 | SNP_BASE | RW snoopable region base (byte address, low 4 GiB) |
0x08 | SNP_LIMIT | RW snoopable region limit (exclusive) |
0x0C | STATUS | RO [0]=slots_active [3:1]=write-FSM state [6:4]=err_code[2:0] [7]=err_valid |
Getting Started
// Minimal instantiation
chi_hn_f_v4 #(
.ADDR_W(6)
) u_chi_hn_f_v4 (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);
Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.