CHI Interconnect & Coherency

CHI Home Node

chihnfv7 is a synthesizable SystemVerilog AMBA 5 CHI Home Node (HN-F): a pipelined,

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ASIL-B

target

90.69%

SPFM

89.60%

LFM

PASS

FMEDA

11.1K

gates

0.7.0

version

The deliverable

What you’re licensing

chihnfv7 is a synthesizable SystemVerilog AMBA 5 CHI Home Node (HN-F): a pipelined, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

chi_hn_f_v7 is a synthesizable SystemVerilog AMBA 5 CHI Home Node (HN-F): a pipelined, N_TXN-deep point-of-coherency/point-of-serialization that layers per-request QoS-priority arbitration onto the catalog’s DCT sharer-vector coherent-read pipeline, with built-in ASIL-B safety instrumentation.

Key Features

QoS-priority grant of every shared HN-F resource: the TXSNP snoop grant, the SN-F memory-read issue, and the TXDAT CompData grant each pick the live slot with the strictly-highest sl_qos; a tie falls back to the lowest slot index (byte-identical to chi_hn_f_v6)
4-bit chi_rxreq_qos latched once per slot at RXREQ accept (sl_qos) and held for that transaction’s lifetime — it cannot be changed mid-flight
Inherited DCT dirty-data forwarding (v6): a dirty SnpRespData is forwarded straight to the requester and the SN-F memory read is skipped
Inherited sharer-vector directory + multi-snoop loop (v5): ReadShared adds a sharer (downgrading a unique owner via SnpShared first); ReadUnique SnpUnique-invalidates every other sharer one at a time per slot
Inherited per-line hazard serialization (v4/v5): a new request whose address matches an already-active slot stalls rather than racing it
Per-slot data-at-rest SECDED (ecc_pkg 64-bit tier) over both memory- and DCT-sourced fills: corrects a single-bit upset in the forwarded CompData, flags a double-bit as err_code 2
Full ASIL-B overlay: config + request-address parity (err_code 1), directory + data-at-rest parity (err_code 2), SN-F RespErr propagation (err_code 3), outstanding-transaction watchdog that also bounds QoS-arbitration starvation (err_code 4), write-FSM complementary diverse-DMR (err_code 9)

Standards & Compliance

Arm AMBA 5 CHI (Issue E); ISO 26262 ASIL-B SEooC (SPFM 90.69%, LFM 89.60%, PMHF 2.07×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.69% · LFM 89.60% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (accept requests) [1]=SNOOP_EN (coherent snooping)
`0x04`	SNP_BASE	RW snoopable region base (byte address, low 4 GiB)
`0x08`	SNP_LIMIT	RW snoopable region limit (exclusive)
`0x0C`	STATUS	RO [0]=slots_active [3:1]=write-FSM state [6:4]=err_code[2:0] [7]=err_valid

Getting Started

// Minimal instantiation
chi_hn_f_v7 #(
  .ADDR_W(6)
) u_chi_hn_f_v7 (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CHI Home Node?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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