CHI Interconnect & Coherency

CHI Home Node — Pipelined DCT + Writeback/Eviction (HN-F v8)

The production-tier, highest-throughput member of the catalog’s CHI Home Node family — pipelined, DCT-forwarding, and directory-eviction-correct…

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ASIL-B

target

90.30%

SPFM

89.44%

LFM

PASS

FMEDA

19.6K

gates

2.33.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

CHI Home Node — Pipelined DCT + Writeback/Eviction (HN-F v8) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

The production-tier, highest-throughput member of the catalog’s CHI Home Node family — pipelined, DCT-forwarding, and directory-eviction-correct… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Catalog #MC-2 (design iteration v11) · chi_hn_f_v8 · ASIL-B SEooC

The production-tier point-of-coherency + point-of-serialization for a snoopable region of an AMBA 5 CHI (Issue E-class) interconnect.

Key Features

N_TXN (default 2) pipelined outstanding coherent-read slots, each independently sequencing lookup → snoop(s) → fill → completion, with a per-line hazard interlock stalling a new request against any active slot’s address
Sharer-vector directory (DIR_ENTRIES=16 default, fully-associative, even parity): ReadShared adds a sharer (downgrading a unique owner via SnpShared first); ReadUnique runs a per-slot multi-snoop SnpUnique invalidate loop against every other sharer
Direct Cache Transfer: a snooped owner’s dirty SnpRespData is forwarded straight to the requester, skipping the memory read; one per-slot buffer + SECDED codec covers both the memory- and DCT-sourced fill
Writeback-on-downgrade (O_WB): a ReadShared downgrade of a dirty owner writes the forwarded line back to memory before completion, so a later ReadNoSnp or eviction reads a fresh copy instead of stale memory
Eviction snoop-back (O_EVSNP/O_EVSNPW/O_EVWB): a coherent miss reclaiming a round-robin victim that is still valid and uniquely (dirty-)owned snoops that victim back and writes the recovered line to memory before the new line is fetched
ASIL-B: config + request-address even parity (err_code 1), per-slot held-line SECDED + directory sharer-vector parity (err_code 2), SN-F read-error-to-RespErr propagation (err_code 3), outstanding-transaction watchdog (err_code 4), write-FSM complementary diverse-DMR shadow (err_code 9)
Verified by a golden-model coherence scoreboard (make chi_hn_f_v8), a dedicated eviction proof (make chi_evict), and formal bmc+cover (make formal_chi_hn_f_v8)

Standards & Compliance

Arm AMBA 5 CHI (Issue E); ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 90.30% · LFM 89.44% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
chi_hn_f_v8 #(
 .ADDR_W(6)
) u_chi_hn_f_v8 (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CHI Home Node — Pipelined DCT + Writeback/Eviction (HN-F v8)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space