CHI Interconnect & Coherency

CHI Performance Monitor

chiperfmon is a synthesizable SystemVerilog non-intrusive tap on a CHI Home Node’s RXREQ/TXDAT path that measures per-transaction request-to-data…

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ASIL-B

target

92.10%

SPFM

90.52%

LFM

PASS

FMEDA

3.1K

gates

0.4.0

version

The deliverable

What you’re licensing

chiperfmon is a synthesizable SystemVerilog non-intrusive tap on a CHI Home Node’s RXREQ/TXDAT path that measures per-transaction request-to-data… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

chi_perf_mon is a synthesizable SystemVerilog non-intrusive tap on a CHI Home Node’s RXREQ/TXDAT path that measures per-transaction request-to-data latency — an accepted request in, the returned CompData out — without ever driving the two channels it observes.

Key Features

Non-intrusive RXREQ/TXDAT tap — all six CHI-side ports (chi_rxreq_flitv/lcrdv/txnid, chi_txdat_flitv/lcrdv/txnid) are inputs, so the monitor can never stall, corrupt, or otherwise perturb the coherent traffic it observes
Per-transaction request-to-data latency via an N_PEND-deep (default 8) TxnID-keyed pending table; matching by TxnID (not arrival order) handles out-of-order TXDAT completions natively
Running min/max, a 32-bit accumulator + count (software-computed mean), a 4-bucket latency histogram (<16/<64/<256/≥256 cycles), and an outstanding-request high-watermark, all read out over APB4
CTRL.EN gates measurement and CTRL.CLR is a self-clearing write pulse that zeroes every counter and the pending table in one cycle
ASIL-B config-register even parity (err_code 1) and an inline-SECDED-protected latency accumulator that self-corrects a single-bit upset on read-out and flags a double-bit one (err_code 2)
Shared bus-hang watchdog trips err_code 4 if the pending table stays non-empty for TIMEOUT_CYCLES (default 65535) cycles — a request whose data never returns; a complementary diverse-DMR shadow on the outstanding count catches an SEU/stuck-at with err_code 9
FMEDA ASIL-B PASS — SPFM 92.10%, LFM 90.52%, PMHF 5.17×10⁻⁹/h — with the pending-count DMR invariant formally proven (formal/chi_perf_mon.sby)

Standards & Compliance

Arm AMBA 5 CHI (Issue E) RXREQ/TXDAT channel tap; ISO 26262 ASIL-B SEooC (SPFM 92.10%, LFM 90.52%, PMHF 5.17×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.10% · LFM 90.52% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (measure) [1]=CLR (pulse: zero all counters)
`0x0C`	STATUS	RO [7:0]=outstanding [15:8]=high-watermark [10:8?] err in [11:8]
`0x10`	LAT	RO [15:0]=lat_min [31:16]=lat_max
`0x14`	ACC	RO 32-bit latency accumulator (SECDED-corrected)
`0x18`	CNT	RO 32-bit completed-transaction count (mean = ACC/CNT)

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
chi_perf_mon #(
  .ADDR_W(6)
) u_chi_perf_mon (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CHI Performance Monitor?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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