System, Safety & Compute

CLINT

A RISC-V Core-Local Interruptor (CLINT) delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

92.50%

SPFM

90.00%

LFM

PASS

FMEDA

1.3K

gates

0.1.0

version

The deliverable

What you’re licensing

A RISC-V Core-Local Interruptor (CLINT) delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A RISC-V Core-Local Interruptor (CLINT) delivered as synthesizable SystemVerilog soft-IP. It provides the machine-timer (mtime / mtimecmp → timer_irq) and machine-software interrupt (msip → sw_irq) required by the RISC-V privileged architecture, accessed over an APB4 slave interface.

Key Features

64-bit free-running mtime counter incremented by an external tick_i strobe, decoupled from the core clock; software may also preset it directly via MTIME_LO/MTIME_HI (0x10/0x14)
Per-hart 64-bit mtimecmp (MTIMECMP_LO/HI, 0x08/0x0C) drives timer_irq_o = (mtime >= mtimecmp); resets to all-ones so no spurious timer interrupt can fire before firmware programs it
Per-hart 1-bit MSIP register (0x00) drives sw_irq_o for software/inter-hart interrupts; both interrupt outputs are level-sensitive, wired directly to the hart’s mip.MTIP/mip.MSIP
Complementary-redundant DMR shadow on the mtime time base (mtime_cmpl = ~mtime, KEEP_ATTR-protected through synthesis) flags a stuck or skewed counter as err_code 9
Even parity over mtimecmp and msip, recomputed on every APB write, flags a corrupted compare threshold or software-IRQ bit as err_code 1
Zero-wait-state APB4 slave (p_pready = p_psel & p_penable, p_pslverr tied 0) with a 5-register, 4-byte-stride map spanning 0x00-0x14
Gate-level stuck-at fault-injection measured 100% single-point-fault detection across 418 flop fault sites, substantiating the FMEDA’s estimated 90-95% per-region diagnostic coverage

Standards & Compliance

RISC-V Privileged Architecture (CLINT mtime/mtimecmp/msip); companion to the RISC-V PLIC and ACLINT specifications; ISO 26262 ASIL-B SEooC (SPFM 92.50%, LFM 90.00%, PMHF 1.84×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.50% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	MSIP	[0] software-interrupt pending (R/W)
`0x08`	MTIMECMP_LO	timer compare, low 32 bits (R/W)
`0x0C`	MTIMECMP_HI	timer compare, high 32 bits (R/W)
`0x10`	MTIME_LO	timer value, low 32 bits (R/W)
`0x14`	MTIME_HI	timer value, high 32 bits (R/W)

Getting Started

// Minimal instantiation
clint #(
  .ADDR_W(6)
) u_clint (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CLINT?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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