Cryptography & Data Integrity

CRC Accelerator

A programmable multi-polynomial CRC accelerator delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

92.50%

SPFM

90.00%

LFM

PASS

FMEDA

2.4K

gates

1.0.0

version

The deliverable

What you’re licensing

A programmable multi-polynomial CRC accelerator delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A programmable multi-polynomial CRC accelerator delivered as synthesizable SystemVerilog soft-IP. It offloads byte-serial CRC computation to hardware with a fully configurable polynomial, initial value, reflect (LSB-first) vs normal (MSB-first) bit order, and final output XOR.

Key Features

Configurable polynomial (32 / 16 / 8-bit width)
Programmable init, reflect-in, reflect-out, final-XOR
One 32-bit word per cycle throughput
Config-register parity (err_code 1)
APB4 slave — DATA / POLY / SEED / RESULT registers
Fully combinational — zero pipeline latency

Standards & Compliance

IEEE 802.3 CRC-32, CRC-16-CCITT, CRC-8

Functional Safety

ASIL-B (SEooC) · SPFM 92.50% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=REFLECT (1=LSB-first/right-shift, 0=MSB-first/left-shift)
`0x04`	POLY	generator polynomial (write in the form matching REFLECT)
`0x08`	INIT	initial register value 0x0C XOROUT final output XOR
`0x10`	CMD	W1: [0]=RESET (crc <- INIT) 0x14 DATA write byte[7:0] -> fold one byte
`0x18`	CRC	RO: crc ^ XOROUT (result) 0x1C RAW RO: bare crc register

Getting Started

// Minimal instantiation
crc #(
  .ADDR_W(6)
) u_crc (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CRC Accelerator?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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