Timers, Clocks & I/O

Clock-Reset-Generator / Power-Management Controller (CRG)

The SoC’s digital clock/reset/power spine — glitch-free clock gating, an ordered reset sequencer, and a low-power handshake, all ASIL-B instrumented.

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ASIL-B

target

99.00%

SPFM

95.00%

LFM

PASS

FMEDA

782

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Clock-Reset-Generator / Power-Management Controller (CRG) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

The SoC’s digital clock/reset/power spine — glitch-free clock gating, an ordered reset sequencer, and a low-power handshake, all ASIL-B instrumented. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

crg is the clock-reset-generator / power-management controller (CRG/PMU) that forms the SoC’s clock/reset/power spine — the digital hub every other domain’s clock enable, reset release, and power state passes through.

Key Features

Glitch-free per-domain clock enable: clk_en[d] = software enable AND domain-out-of-reset AND SoC-in-RUN — the gate can only change while the domain clock is already off
Ordered reset sequencer: rst_n_o[d] deasserted domain-by-domain 0..NDOM-1 under a programmed per-domain hold count; disabling the sequencer re-asserts every reset
First-cause-wins reset-cause capture: POR / watchdog / software / lockstep, latched and read back one-hot in STAT[7:4]
RUN / SLEEP / DEEP_SLEEP power handshake: broadcasts pwr_req, advances only once every domain’s pwr_ack matches, wake forces an immediate return to RUN
Config-register even parity on CR/SEQHOLD/TIMEOUT/PWRCR (err_code 1)
Illegal power-transition (no RUN<->DEEP_SLEEP jump) and reset-order plausibility check (err_code 3), handshake/sequence timeout (err_code 4)
KEEP_ATTR complementary DMR on the reset-sequencer FSM and power-mode state (err_code 9), with fi_seq_xor/fi_pwr_xor DFT fault injection to prove the path

Standards & Compliance

AMBA APB4; ISO 26262 Part 5 diagnostic patterns (config parity, sequence/handshake timeout, complementary DMR); ISO 26262 ASIL-B SEooC (SPFM 99.00%, LFM 95.00%, PMHF 1.57e-10/h)

Functional Safety

ASIL-B (SEooC) · SPFM 99.00% · LFM 95.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CR	[1]=SEQ_GO (write 1: launch the reset deassert sequence) [0]=SEQ_EN (sequencer enable)
`0x04`	SEQHOLD	per-domain reset hold count, HOLD_W bits per domain, packed LSB=domain0
`0x08`	TIMEOUT	reference cycles a domain may take to pwr_ack / be sequenced before err_code 4
`0x0C`	PWRCR	[1:0]=PWR_REQ requested power mode (0=RUN 1=SLEEP 2=DEEP_SLEEP)
`0x10`	STAT	[0]=SEQ_BUSY [1]=SEQ_DONE(W1C) [2]=TMO_F(W1C) [3]=ILL_F(W1C) [7:4]=reset-cause one-hot reset cause: [4]=POR [5]=WDOG…

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
crg #(
 .ADDR_W(6)
) u_crg (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the housekeeping layer every SoC needs — timing, watchdogs, reset, and I/O.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Clock-Reset-Generator / Power-Management Controller (CRG)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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