Display, Imaging & Multimedia

MIPI CSI-2 Receiver

A synthesizable SystemVerilog CSI-2 Receiver IP that implements the MIPI CSI-2 v2.0 packet protocol layer above an external MIPI D-PHY Rx hard macro.

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ASIL-B

target

91.00%

SPFM

89.98%

LFM

PASS

FMEDA

2.4K

gates

0.1.0

version

The deliverable

What you’re licensing

A synthesizable SystemVerilog CSI-2 Receiver IP that implements the MIPI CSI-2 v2.0 packet protocol layer above an external MIPI D-PHY Rx hard macro. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A synthesizable SystemVerilog CSI-2 Receiver IP that implements the MIPI CSI-2 v2.0 packet protocol layer above an external MIPI D-PHY Rx hard macro.

Key Features

1 or 2 D-PHY lanes (LANES = 1|2)
Short + long packet decode (RAW8/10/12, YUV422, RGB888)
Hamming(6,1) header ECC — SBE corrected, DBE flagged
CRC-16/CCITT payload integrity
4-bit virtual-channel filter

Standards & Compliance

MIPI CSI-2 v2.0, MIPI D-PHY

Functional Safety

ASIL-B (SEooC) · SPFM 91.00% · LFM 89.98% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [2:1]=LANES, [6:3]=VC_FILTER, [7]=RESET
`0x04`	STATUS	RO [0]=FRAME_ACTIVE, [1]=LINE_ACTIVE, [2]=FIFO_EMPTY, [3]=ECC_ERR, [4]=CRC_ERR
`0x08`	INTR	W1C [0]=FRAME_START, [1]=FRAME_END, [2]=ECC_ERR, [3]=CRC_ERR, [4]=FIFO_OVF
`0x0C`	INTR_EN	RW same bits
`0x10`	FRAME_CNT	RO frames received

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
csi2_rx #(
  .ADDR_W(6)
) u_csi2_rx (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in instrument clusters, camera pipelines, and safety-monitored display paths.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MIPI CSI-2 Receiver?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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