CHI Interconnect & Coherency

CXL.mem Type-3 Memory-Expander Endpoint

The CXL twin of chi_sn_f — coherent memory expansion with end-to-end SECDED.

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ASIL-B

target

94.16%

SPFM

90.00%

LFM

PASS

FMEDA

6.3K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The CXL twin of chi_sn_f — coherent memory expansion with end-to-end SECDED. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

cxl_mem_dev is a CXL.mem Type-3 memory-expander endpoint — the device side of a Compute Express Link memory-expansion port.

Key Features

Credited M2S Req / RwD + S2M DRS / NDR channels — credit conservation formally proven
HDM address decode + full-line MemRd / MemWr
End-to-end per-64b SECDED — SBE correct, DBE detect → CXL poison out (err_code 2)
Poison propagation + viral containment on uncorrectable errors
Outstanding-FIFO + viral diverse-DMR (err_code 9) + config/HDM parity (err_code 1)
Reuses the chi_sn_f DRAM-facing port → sn_to_ddr5 / ddr5_ctrl back end

Standards & Compliance

CXL 2.0 (CXL.mem, Type-3 device)

Functional Safety

ASIL-B (SEooC) · SPFM 94.16% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN [1]=VIRAL_EN [2]=T2_EN(Type-2 HDM-D mode)
`0x04`	HDM_BASE	RW device-physical base of the HDM range (line-aligned)
`0x08`	HDM_SIZE	RW size of the HDM range (lines); a request outside -> S2M MemData-NXM / Cmp-err
`0x0C`	STATUS	RO [0]=busy [3:1]=outstanding [6:4]=err_code[2:0] [7]=err_valid [8]=viral
`0x10`	RAS_CE	RO correctable-error (SBE) count (saturating)

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
cxl_mem_dev #(
 .ADDR_W(6)
) u_cxl_mem_dev (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in multi-core compute clusters that need cache coherency with a defensible ordering proof.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in CXL.mem Type-3 Memory-Expander Endpoint?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space