CTR\_DRBG

Overview

The DRBG IP is a CTR_DRBG (NIST SP 800-90A Rev.1 §10.2) built on an AES-256 block cipher core, delivered as an APB4 slave with ASIL-B safety instrumentation.

Key Features

• CTR_DRBG per NIST SP 800-90A §10.2 on an AES-256 core: SEED latches Key(256b)/V(128b) from a 480-bit entropy bank, GENERATE returns one 128-bit block via a full 14-round AES-256 encryption of V+1.
• Per-word even parity across every stored register — Key, V, the 15-word ENTROPY bank, and OUT — checked every cycle and reported as err_code 1.
• Dual-rail lockstep on both the AES datapath (state/round-key/schedule) and the control FSM/round counter, so a corrupted control sequence is caught, not just a corrupted datapath value; mismatch reported as err_code 9.
• Hardware known-answer self-test (CTRL.SELFTEST, bit 3): runs a fixed vector through the live AES pipeline and compares it to an external golden value, catching common-mode faults dual-rail comparison structurally cannot see; mismatch reported as err_code 3.
• Measured ASIL-B (SEooC) PASS: SPFM 97.55%, LFM 100.00%, PMHF 1.20×10⁻⁸/h from gate-level fault injection.
• Software-mediated entropy path (no hardware TRNG connection) with a write-only ENTROPY bank that never reads back, and big-endian OUT byte order.
• Firmware-visible reseed governance: a 24-bit generation counter asserts STATUS.RESEED_REQ at 2^24 GENERATE calls, tighter than the FIPS 2^48 ceiling.

Standards & Compliance

NIST SP 800-90A Rev.1 §10.2 (CTR_DRBG), FIPS 197 (AES-256); ISO 26262 ASIL-B (SEooC), measured PASS

Functional Safety

ASIL-B (SEooC) · SPFM 97.55% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Getting Started

// Minimal instantiation
drbg #(
  .ADDR_W(6)
) u_drbg (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.