Drone, Robotics & UAV Safety

DroneCAN / Cyphal Transport Engine

Hardware DroneCAN/UAVCAN-v0 + Cyphal/CAN transport layer — transfer CRC + toggle-bit integrity for UAV avionics CAN buses, ASIL-B.

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ASIL-B

target

92.10%

SPFM

88.56%

LFM

Informational

FMEDA

27.0K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

Hardware DroneCAN/UAVCAN-v0 + Cyphal/CAN transport layer — transfer CRC + toggle-bit integrity for UAV avionics CAN buses, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

dronecan is a synthesizable DroneCAN/UAVCAN-v0 and Cyphal/CAN transport-layer engine for CAN-bus avionics nodes — the protocol spoken across UAV flight-controller buses to ESCs, GNSS receivers, servos, and power modules.

Key Features

Hardware RX reassembly: multi-frame transfers rebuilt from tail-byte SOT/EOT/toggle/transfer-id, with CRC-16-CCITT transfer-CRC recompute + compare — a corrupted or mis-sequenced transfer is never marked ready (err_code 3)
Hardware TX segmentation: host loads a payload + length/transfer-id; the engine appends the transfer CRC and chops it into CAN frames with correct tail bytes automatically
Two protocols, one APB4-selectable engine: DroneCAN/UAVCAN-v0 and Cyphal/CAN share the same tail-byte transport machine, differing only in the 29-bit ID header layout (CTRL.PROTO)
Reassembly timeout watchdog (TOLIMIT) flags a stalled/mid-transfer sender instead of wedging the reassembly context (err_code 4)
SECDED-protected reassembly buffer (fifo_ecc) corrects a single-bit upset transparently and flags a double-bit error (err_code 2)
Config-register even parity (CTRL/NODEID/FILTER/TOLIMIT, err_code 1) plus a KEEP_ATTR complementary-DMR shadow of the reassembly FSM (err_code 9), each provable via a dedicated fi_* fault-injection input
ASIL-B pre-sign-off FMEDA: SPFM 92.10%, LFM 88.56%, PMHF 4.02×10⁻⁸/h — PASS against the ASIL-B target, with a documented redundant-bus deployment path for safety-critical flight-control loops

Standards & Compliance

DroneCAN/UAVCAN v0 transport, Cyphal/CAN, AMBA APB4-lite; ISO 26262 ASIL-B SEooC (SPFM 92.10%, LFM 88.56%, PMHF 4.02×10⁻⁸/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 92.10% · LFM 88.56% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=RX_EN [2]=TX_EN [3]=PROTO (0=DroneCAN/UAVCANv0,1=Cyphal/CAN)
`0x04`	NODEID	[6:0] this node’s source node-id
`0x08`	FILTER	[15:0] subscribed message-type-id filter (match -> accept; 0xFFFF = accept all)
`0x0C`	TXCTRL	[7:0]=payload length (bytes) [12:8]=tx transfer-id; a write triggers a TX transfer
`0x10`	TXDATA	WO [7:0] push one payload byte into the TX byte buffer

…5 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
dronecan #(
 .ADDR_W(6)
) u_dronecan (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in UAV flight controllers and robotics platforms operating under a functional-safety mandate.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in DroneCAN / Cyphal Transport Engine?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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