Display, Imaging & Multimedia

MIPI DSI Host Controller

MIPI DSI protocol-layer host controller for command-mode and video-mode display links, ASIL-B safety-instrumented and D-PHY hard-macro agnostic.

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ASIL-B

target

93.75%

SPFM

90.00%

LFM

PASS

FMEDA

4.6K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

MIPI DSI protocol-layer host controller for command-mode and video-mode display links, ASIL-B safety-instrumented and D-PHY hard-macro agnostic. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A synthesizable SystemVerilog MIPI DSI (Display Serial Interface) Host Controller — a digital-only protocol-layer packetizer that frames command-mode DCS writes and video-mode RGB888 pixel streams (ECC + CRC-16, 8-entry command FIFO) behind an APB4 configuration interface, and hands the framed bytes to an external MIPI D-PHY Tx hard macro.

Key Features

Command mode: DCS short write (0/1-param, DI 0x05/0x15) and DCS long write (DI 0x39) with CRC-16/CCITT payload protection, auto-packetised from an 8-entry command FIFO by CMD_LEN/CMD_DT
Video mode: packed 24-bit RGB888 pixel stream (DI 0x3E) armed by vsync/hsync/de edges, with word count computed from VID_CFG pixel timing
Full MIPI DSI Hamming ECC on every packet header and CRC-16/CCITT on every long-write and pixel-stream payload
Video data plane crosses clock domains through an internal asynchronous cdc_fifo (16-deep) that moves the {hsync,vsync,de,data} word atomically, eliminating multi-bit tearing across the pixel-to-system clock boundary
ASIL-B safety overlay: even-parity on CTRL/CMD_LEN/CMD_DT (err_code 1), command-FIFO overflow detection (err_code 3), and complementary-DMR lockstep on both the command and video packetiser FSMs (err_code 9)
APB4 slave: 8 × 32-bit registers (CTRL, STATUS, INTR, INTR_EN, CMD_FIFO, CMD_LEN, CMD_DT, VID_CFG), zero wait states, W1C interrupt register feeding a single dsi_irq_o
FMEDA-verified ASIL-B SEooC: SPFM 93.75%, LFM 90.00%, PMHF 5.37×10⁻⁹/h against target; parameterisable LANES (1–4) and ADDR_W

Standards & Compliance

MIPI DSI (Display Serial Interface) protocol specification; ISO 26262 ASIL-B SEooC (SPFM 93.75%, LFM 90.00%, PMHF 5.37×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.75% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x05`	—	DCS short write (0 param) : 4 bytes: [DI][P0=cmd][P1=0][ECC]
`0x15`	—	DCS short write (1 param) : 4 bytes: [DI][P0=cmd][P1=param][ECC]
`0x39`	—	DCS long write : header(4)+payload[N]+CRC16(2)
`0x3E`	—	Packed pixel stream, 24-bit RGB888
`0x00`	CTRL	RW [0]=EN [1]=MODE(0=CMD,1=VID) [3:2]=LANES [4]=LP_EN [5]=RESET

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
dsi_host #(
 .ADDR_W(6)
) u_dsi_host (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in instrument clusters, camera pipelines, and safety-monitored display paths.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MIPI DSI Host Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space