DShot Digital ESC Protocol Generator

What it is

esc_dshot is a synthesizable SystemVerilog soft-IP that generates the DShot digital ESC (Electronic Speed Controller) protocol for brushless drone/UAV motor control, with optional bidirectional DShot eRPM-telemetry decode.

Key Features

• DShot 150/300/600/1200 bit rates, APB-selectable (CTRL.RATE), plus an explicit DIVCFG clocks-per-bit override for arbitrary reference clocks
• 16-bit frame per channel — 11-bit throttle + 1 telemetry-request bit + 4-bit CRC (CRC4 = XOR of the three nibbles of the 12-bit {throttle,tlm} value) — shifted out MSB-first on a shared bit grid
• NUM_MOTORS independent channels (default 4), each with its own dshot_o/dshot_oe pin pair and 11-bit throttle register, so no motor’s command shares another’s wiring
• Per-channel ARM enable plus a global CTRL.EN — a disarmed channel never spins, and a spin command reaching it is caught as a plausibility fault (err_code 3), not silently applied
• Optional bidirectional DShot (BIDIR parameter): tri-states the line after each frame and decodes the GCR-encoded eRPM telemetry reply, CRC-checked before STATUS.TLM_VALID sets
• ASIL-B safety: config-register even parity (err_code 1); per-frame CRC4 generate/check + throttle-range/arming-interlock plausibility + telemetry CRC (err_code 3); complementary-DMR on the bit-period/bit-index timing counter (err_code 9)
• fi_cfg_par/fi_crc_bad/fi_cnt_xor DFT inputs prove each diagnostic path in simulation and on a tester; all config registers (ARM included) reset to the safe, disarmed, zero-throttle state

Standards & Compliance

DShot150/300/600/1200 digital ESC protocol (+ bidirectional eRPM telemetry); APB4-lite host interface; ISO 26262 ASIL-B SEooC (SPFM 92.50%, LFM 90.00%, PMHF 2.49×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 92.50% · LFM 90.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
esc_dshot #(
 .ADDR_W(6)
) u_esc_dshot (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.