System, Safety & Compute

Pulse-Tested E-Stop Safety Input

Dual-channel, pulse-tested emergency-stop interface that proves the button and its wiring healthy every cycle and gates the actuation cutoff with a…

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ASIL-B

target

93.39%

SPFM

91.26%

LFM

PASS

FMEDA

825

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Pulse-Tested E-Stop Safety Input routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Dual-channel, pulse-tested emergency-stop interface that proves the button and its wiring healthy every cycle and gates the actuation cutoff with a… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A synthesizable soft-IP that forms the last-resort actuation cutoff path from a safety emergency-stop button to a SoC’s power/enable chain, continuously proving the button and its wiring are healthy rather than trusting a bare contact closure.

Key Features

2x NC channels pulse-tested with two independent-seed/tap LFSR patterns, cross-monitored to catch a cross-short or short-to-rail that a plain contact-closure input cannot see
1x NO antivalent contact check (REQUIRE\_NO) for stuck/absent-switch detection, plus a programmable confirmation window (WIN) that debounces contact bounce before declaring a state
Fail-safe safe\_out: triple-redundant (TMR) registered permit, 0 at reset and 0 on any latched fault, wired straight into the actuator/contactor enable outside the config plane
Voter/latch self-check: a single fault in the safe\_out decision register is masked by the 2-of-3 vote and reported as a latent fault (err\_code 9), not silently lost
ASIL-D control-path diagnostic: complementary-redundant (DMR) pulse-test tick counter catches an FSM/counter fault feeding the same err\_code 9
Config-register even parity (err\_code 1) and latched channel/discrepancy/antivalence faults (err\_code 3) escalate through the shared safety\_monitor, with maskable estop\_irq
Measured FMEDA PASS ASIL-B — SPFM 93.39%, LFM 91.26%, PMHF 1.03×10⁻⁹/h — APB4 register map for CTRL/STATUS/PULSEDIV/ERR/IER/ISR

Standards & Compliance

APB4 slave interface; IEC 60204-1 e-stop category-0/1 stop practice (integrator layer); ISO 26262 ASIL-B SEooC (SPFM 93.39%, LFM 91.26%, PMHF 1.03×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.39% · LFM 91.26% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
estop #(
 .ADDR_W(6)
) u_estop (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Pulse-Tested E-Stop Safety Input?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space