Serial, Networking & Storage

Ethernet PFC Link-Endpoint Controller

Priority-based Flow Control responder/originator — 8-priority, lockstep-safe.

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ASIL-B

target

90.20%

SPFM

88.80%

LFM

PASS

FMEDA

4.4K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Ethernet PFC Link-Endpoint Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Priority-based Flow Control responder/originator — 8-priority, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable Ethernet Priority-based Flow Control (PFC) link-endpoint controller soft-IP — a standalone digital IP that taps an RX byte-stream to detect and act on incoming PFC control frames, and can generate its own PFC frames on a TX byte-stream, matching this catalog’s “digital-only, connects to an external MAC/PHY” convention already used for dp_link/csi2_rx.

Key Features

Passive RX tap — watches ALL RX traffic, reacts only to PFC-shaped frames, never gates/backpressures the stream
Byte-exact PFC MAC Control frame detection (DA 01:80:C2:00:00:01 + Ethertype 0x8808 + Opcode 0x0101)
8 independent per-priority RX quanta-countdown timers with live pause_active status + REFRESH/0-quanta-immediate-release semantics
CSR-triggered TX PFC frame generation under a standard valid/ready streaming handshake
Diverse-DMR FSM lockstep spanning RX capture + TX generation FSMs PLUS free-running counters (err_code 9)
Config + datapath register parity, incl. the RX staging path (err_code 1 / 2)

Standards & Compliance

IEEE 802.1Qbz / 802.3x Annex 31D Priority-based Flow Control (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification)

Functional Safety

ASIL-B (SEooC) · SPFM 90.20% · LFM 88.80% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN [1]=SEND_PFC (self-clearing command trigger)
`0x04`	STATUS	RO/W1C [7:0]=PAUSE_ACTIVE mirror (RO) [8]=PROTO_ERR (W1C, mirrors err_code 3) [9]=TX_BUSY (RO)
`0x08`	ENABLE_VEC	RW [7:0] = priority-enable vector for the NEXT generated PFC frame
`0x0C..0x28`	QUANTA0..7	RW [15:0] each, 4-byte stride = per-priority pause-quanta for the NEXT generated frame (8 registers)
`0x2C..0x48`	RXQ_RB0..7	RO [15:0] each, 4-byte stride = CURRENT remaining RX countdown for priority N (8 registers, live diagnostic mirror)

…1 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
eth_pfc #(
 .ADDR_W(6)
) u_eth_pfc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Ethernet PFC Link-Endpoint Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space