System, Safety & Compute

Fault Collection & Control Unit (FCCU)

fccu is the catalog’s central fault aggregator. It collects the errvalid outputs of every other IP (or any other fault source) on up to NSRC hardware…

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ASIL-B

target

99.25%

SPFM

100.00%

LFM

PASS

FMEDA

1.8K

gates

0.1.0

version

The deliverable

What you’re licensing

fccu is the catalog’s central fault aggregator. It collects the errvalid outputs of every other IP (or any other fault source) on up to NSRC hardware… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

fccu is the catalog’s central fault aggregator. It collects the err_valid outputs of every other IP (or any other fault source) on up to NSRC hardware fault lines, latches them stickily in a priority-encoded register, and drives a single external critical-fault pin (fault_out_o) plus a non-critical alarm output (alarm_o).

Key Features

N-source sticky fault latches with DMR self-parity
Priority-encoded FAULTID output + fault-output pin
APB enable and reaction-mask registers per source
Self-parity DMR on fault-latch array (err_code 9)
Fault-injection registers for FMEDA / self-test
SPFM 93.75% ASIL-B PASS

Standards & Compliance

ISO 26262 Part 5 — fault collection / safety monitoring unit (FCCU pattern)

Functional Safety

ASIL-B (SEooC) · SPFM 99.25% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	ENABLE	[NSRC-1:0] R/W per-source enable mask
`0x04`	STATUS	[NSRC-1:0] RO sticky fault bits
`0x08`	CLEAR	[NSRC-1:0] W1C write 1 clears that sticky bit
`0x0C`	REACTION	[NSRC-1:0] R/W 1=critical (drives fault_out), 0=alarm only
`0x10`	INJECT	[NSRC-1:0] W1S write 1 sets sticky (fault injection / SMU)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
fccu #(
  .ADDR_W(6)
) u_fccu (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Fault Collection & Control Unit (FCCU)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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