Serial, Networking & Storage

FlexRay Dual-Channel TT Controller

flexray is an ISO 17458 / FlexRay 3.0.1 time-triggered communication controller (TT-CC): a synthesizable SystemVerilog protocol engine for the…

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ASIL-B

target

94.05%

SPFM

90.00%

LFM

PASS

FMEDA

8.4K

gates

1.0.0

version

The deliverable

What you’re licensing

flexray is an ISO 17458 / FlexRay 3.0.1 time-triggered communication controller (TT-CC): a synthesizable SystemVerilog protocol engine for the… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

flexray is an ISO 17458 / FlexRay 3.0.1 time-triggered communication controller (TT-CC): a synthesizable SystemVerilog protocol engine for the dual-channel (A/B) TDMA static segment, with an APB4-lite slave register interface and built-in ASIL-B safety instrumentation.

Key Features

Dual-channel (A/B) static-segment TDMA engine: 0..63 cycle counter × 0..63 slot counter against a configurable MAX_SLOTS schedule RAM
Channel-redundant transmit — cha_txd/chb_txd mirror the same bit; receive selects one channel (A priority, else B) — no in-RTL cross-channel vote
11-bit header-CRC (poly 0x385) + 24-bit frame-CRC (poly 0x5D6DCB) generate/check plus slot/cycle/length plausibility → err_code 3
SECDED-protected RX frame buffer (fifo_ecc): single-bit corrected transparently, double-bit uncorrectable → err_code 2
Programmable loss-of-sync timeout watchdog (SYNC_TIMEOUT) → err_code 4; even-parity config-register protection → err_code 1
KEEP_ATTR complementary-DMR lockstep on the protocol FSM and slot/cycle counters → err_code 9, with fi_* DFT fault-injection on every mechanism
External TJA1080-class bus driver per channel; cha_bus_active/chb_bus_active feed an external bus-guardian / active-star function (not implemented on-chip)

Standards & Compliance

ISO 17458 / FlexRay 3.0.1; ISO 26262 ASIL-B SEooC (SPFM 94.05%, LFM 90.00%, PMHF 9.41×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 94.05% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=POC_RUN(enable) [1]=CHA_EN [2]=CHB_EN [3]=LOOPBACK [4]=RXPOP(W1 self-clear)
`0x04`	STATUS	[0]=RX_VALID [1]=SYNC_OK [2]=IN_STATIC [5:3]=fsm_state [13:8]=cycle_cnt [14]=RX_FULL [15]=SYNC_SEEN [21:16]=slot_cnt
`0x08`	CFG	[3:0]=STATIC_SLOTS(num static slots,1..MAX) [9:4]=SLOT_TICKS(ticks/slot) [15:10]=NIT_TICKS [16]=SYNC_REQ(require a s…
`0x0C`	TIMING	[15:0]=SYNC_TIMEOUT (cycles w/o a sync frame -> loss-of-sync, err4)
`0x10`	SCHED_IDX	[3:0]=slot index selected for SCHED_DAT access

…7 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
flexray #(
  .ADDR_W(6)
) u_flexray (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in FlexRay Dual-Channel TT Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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