Serial, Networking & Storage

Gigabit Ethernet MAC (GMAC)

Full IEEE 802.3 framing: 7-byte preamble + SFD generation,

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ASIL-B

target

93.05%

SPFM

90.00%

LFM

PASS

FMEDA

3.5K

gates

11.0.0

version

The deliverable

What you’re licensing

Full IEEE 802.3 framing: 7-byte preamble + SFD generation, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

1. Overview

10/100/1000 Mbps Ethernet MAC with Clause-22/45 MDIO management, IEEE 802.3 framing, 802.1Q/802.1ad VLAN, 802.3x PAUSE, IEEE 1588 PTP timestamping, and an optional AXI4-Lite descriptor-DMA TX path.

Key Features

Full IEEE 802.3 framing: 7-byte preamble + SFD generation, CRC-32 FCS computed on TX and verified on RX with jumbo-frame support via a 16-bit TX-length field
Destination-address filter with unicast, broadcast, and promiscuous modes; Clause-22 MDIO master plus a Clause-45 indirect ADDRESS/READ-WRITE sequencer
802.1Q VLAN tag insertion/stripping and 802.1ad Q-in-Q stacked-tag TX insertion / RX stripping; 802.3x PAUSE frame TX generation and RX recognition
IEEE 1588 PTP: a free-running cycle counter latched at TX SFD and RX SFD for firmware-computed propagation-delay / offset arithmetic
Optional AXI4-Lite descriptor-DMA: a dedicated TX master walks a single-descriptor-per-frame ring, and a dedicated RX master scatters received frames across a multi-descriptor ring straight into host memory
Single fabric clock domain with no internal CDC logic — the PHY adapter owns the line-rate clock and its crossing into the MAC’s clk, keeping the framing/CRC datapath fully synchronous
ASIL-B safety: config parity incl. RX-DMA pointer state (err_code 1), TX/RX FIFO SECDED (err_code 2), CRC-32 / descriptor-protocol error (err_code 3), complementary-DMR RX-error + RX-DMA FSM lockstep (err_code 9)

Standards & Compliance

IEEE 802.3 (Ethernet MAC framing, CRC-32 FCS, Clause 22/45 MDIO); IEEE 802.1Q / 802.1ad (VLAN / Q-in-Q); IEEE 802.3x (PAUSE flow control); IEEE 1588 (PTP timestamping); ISO 26262 ASIL-B SEooC (SPFM 93.05%, LFM 90.00%, PMHF 4.64×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.05% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	MAC_CTRL	[0]=TX_EN [1]=RX_EN
`0x04`	MAC_STAT	RO [0]=TX_BUSY [1]=RX_FIFO_NE [2]=RX_ERR [3]=RX_FIFO_FULL
`0x08`	TX_DATA	W byte-push into TX FIFO
`0x0C`	TX_GO	W: write the length and start TX (preamble+SFD+payload+CRC)
`0x10`	RX_DATA	R byte-pop from RX FIFO

…23 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
gmac #(
  .ADDR_W(6)
) u_gmac (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Gigabit Ethernet MAC (GMAC)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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