Timers, Clocks & I/O

General-Purpose I/O

A parameterizable GPIO peripheral delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

981

gates

1.10.0

version

The deliverable

What you’re licensing

A parameterizable GPIO peripheral delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A parameterizable GPIO peripheral delivered as synthesizable SystemVerilog soft-IP.

Key Features

Configurable-width bidirectional I/O
Per-bit DIR / OE / PU / PD register control
Edge-detect interrupt (rising / falling / both)
Parity protection on config registers (err_code 1)
Diverse-DMR FSM lockstep (err_code 9)
Formally verified FSM safety invariant

Standards & Compliance

Generic (ISO 26262 SEooC GPIO pattern)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	DIR	1=output, 0=input 0x20 DSET W1S: dout \|= wdata (atomic set)
`0x04`	DOUT	output data 0x24 DCLR W1C: dout &= ~wdata (atomic clear)
`0x08`	DIN	RO: synchronized input 0x28 DTGL W1T: dout ^= wdata (atomic toggle)
`0x0C`	IER	interrupt enable 0x2C ODE 1=open-drain, 0=push-pull
`0x10`	ISR	interrupt status (w1c) 0x30 PADPU 1=pull-up enable (pad select)

…4 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
gpio #(
  .ADDR_W(6)
) u_gpio (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the housekeeping layer every SoC needs — timing, watchdogs, reset, and I/O.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in General-Purpose I/O?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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