Serial, Networking & Storage

I²C Slave Controller

Addressable I²C slave — open-drain SDA/SCL, ASIL-B lockstep FSM, integration-ready.

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ASIL-B

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

670

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

I²C Slave Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Addressable I²C slave — open-drain SDA/SCL, ASIL-B lockstep FSM, integration-ready. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable 7-bit I2C slave soft-IP — the counterpart to ip/i2c_master. It detects START/STOP, matches its programmed address, ACKs, and exchanges bytes with an external I2C master (host write → RXDATA, host read ← TXDATA) over an open-drain SDA/SCL pair.

Key Features

7-bit address match against a configurable ADDR register; a non-matching address NACKs and releases the bus (silent, multi-drop-safe)
Open-drain sda_oe pull-low enable (no internal pull-up); SCL/SDA double-flopped into clk for metastability-safe edge and START/STOP detection
Master write → RXDATA, with RX_READY and a write-1-to-clear OVERRUN if the prior byte was not read before the next completed
Master read ← TXDATA, shifted out MSB-first with the bus released each byte for the master’s ACK/NACK
No clock stretching in v0.1 (SCL is input-only) — host must service the single-byte buffer at the bus rate
Config-register (CTRL/ADDR) even parity into safety_monitor (err_code 1); latched TXDATA/RXDATA data-byte parity (err_code 2)
Diverse complementary-DMR lockstep across the FSM state, bit counter, and RX/TX shift registers (err_code 9)

Standards & Compliance

NXP I²C-bus Specification UM10204 Rev. 7 (slave/target mode); ISO 26262 ASIL-B SEooC (SPFM 100.00%, LFM 100.00%, PMHF 9.54×10⁻¹⁰/h)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN 0x04 ADDR [6:0]=7-bit slave address
`0x08`	STATUS	[0]=RX_READY [1]=ADDRESSED [2]=OVERRUN(W1C) [3]=RW_DIR
`0x0C`	TXDATA	0x10 RXDATA (read clears RX_READY) 0x14 IER [0]=RX_IE

Getting Started

// Minimal instantiation
i2c_slave #(
 .ADDR_W(6)
) u_i2c_slave (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in I²C Slave Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space