Serial, Networking & Storage

I²S Audio Interface Controller

APB4 I²S master with SECDED/parity/lockstep ASIL-B coverage — the audible-warning and chime delivery path.

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ASIL-B

target

95.10%

SPFM

90.00%

LFM

PASS

FMEDA

3.5K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

I²S Audio Interface Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 I²S master with SECDED/parity/lockstep ASIL-B coverage — the audible-warning and chime delivery path. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable I²S (Inter-IC Sound) audio interface controller delivered as synthesizable SystemVerilog soft-IP. It generates BCK/LRCK as the I²S clock master and serializes/deserializes left-justified stereo PCM audio on an APB4 register interface, with built-in ASIL B safety instrumentation (SECDED-protected FIFOs, config-register parity, diverse-DMR bit-counter lockstep).

Key Features

Master-clock BCK/LRCK generation from a 16-bit PRESCALER (BCK = clk/(2×(PRESCALER+1))), left-justified stereo framing at runtime-selectable 16/24/32-bit word width (CR.DATLEN)
Independent SECDED-protected TX/RX FIFOs (fifo_ecc, depth-8 default) decouple the APB4 DR word interface from the continuous serial bit stream; single-bit upsets corrected in-line, double-bit upsets raise err_code 2
Fail-quiet TX underrun: an empty TX FIFO at a word boundary loads silence (32’h0) instead of repeating stale/corrupted data — the safe failure mode wherever this drives an audible-warning or chime path
Even-parity protection on CR/PRESCALER (err_code 1) and a diverse-DMR complementary shadow counter on the bit-framing engine (err_code 9), both aggregated into the shared safety_monitor
SR.OVR captures a dropped RX capture word but clears silently on the next CR write — must be polled/latched by the integrator before servicing CR
DFT ECC-injection ports (tx_ecc_inj/rx_ecc_inj, 39 bits each) exercise SBE-correct/DBE-detect fault injection in test; tie to 0 in production
APB4 slave, four registers at a 4-byte stride (CR 0x00, SR 0x04, DR 0x08, PRESCALER 0x0C); ASIL-B FMEDA: SPFM 95.10%, LFM 90.00%, PMHF 3.27×10⁻⁹/h

Standards & Compliance

I²S serial audio protocol (Philips/NXP spec, left-justified stereo, 16/24/32-bit); ISO 26262 ASIL-B SEooC (SPFM 95.10%, LFM 90.00%, PMHF 3.27×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 95.10% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
i2s #(
 .ADDR_W(6)
) u_i2s (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in I²S Audio Interface Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space