Serial, Networking & Storage

MIPI I3C Controller (Master + Slave, SDR)

Synthesizable MIPI I3C controller (master) and target (slave) for the shared two-wire SCL/SDA bus,

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ASIL-B

target

90.46%

SPFM

88.68%

LFM

PASS

FMEDA

1.6K

gates

2.33.0

version

The deliverable

What you’re licensing

Synthesizable MIPI I3C controller (master) and target (slave) for the shared two-wire SCL/SDA bus, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

Synthesizable MIPI I3C controller (master) and target (slave) for the shared two-wire SCL/SDA bus, implementing SDR-mode private read/write transfers with the I3C T-bit (odd-parity) replacing the I2C per-byte ACK.

Key Features

SDR private write (controller→target) and read (target→controller) data path with the I3C T-bit (odd parity) replacing the I2C per-byte data ACK; the address byte still uses a conventional ACK
Static 7-bit addressing with a controller-generated SCL via a DIV half-period divisor; open-drain sda_oe wire-AND bus model, with i3c_link demonstrating master + slave on one shared line
Independent APB4 register file per side (4-byte stride): master CTRL/ADDR/TXDATA/RXDATA/CMD/STATUS; slave CTRL/ADDR/STATUS/TXDATA/RXDATA
ASIL-B config-register even parity on CTRL/ADDR (err_code 1) and on the TXDATA/RXDATA data-hold registers (err_code 2), both submodules
Complementary-lockstep DMR across the transfer FSM, bit/byte counters, and TX/RX shift registers (err_code 9, AP_FSM_LOCKSTEP_CLEAN) — identical mechanism on master and slave, aggregated into one safety_monitor per instance
Catalog FMEDA (i3c_link): SPFM 90.46%, LFM 88.68%, PMHF 2.94×10⁻⁹/h — PASS against the ASIL-B target with margin on every metric
Honest v0.1 scope: dynamic address assignment (ENTDAA), CCC, in-band interrupts (IBI), hot-join, and HDR modes are explicitly not implemented — an SDR-private-transfer proof, not a full I3C-compliant stack

Standards & Compliance

MIPI I3C (SDR-mode private read/write, static-addressing subset); I2C-compatible open-drain bus electricals at the address phase; ISO 26262 ASIL-B SEooC (SPFM 90.46%, LFM 88.68%, PMHF 2.94×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.46% · LFM 88.68% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
i3c #(
  .ADDR_W(6)
) u_i3c (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MIPI I3C Controller (Master + Slave, SDR)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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