MIPI I3C Master (SDR)

The i3c_master core is an APB4-mapped MIPI I3C v1.1.1 controller that generates SCL itself and drives one private read/write transfer at a time — START, {address[6:0], R/nW}, address ACK, one data byte with the I3C T-bit (odd parity) replacing the I²C data-ACK, and STOP — over a shared open-drain SCL/SDA pair modelled through sda_oe.

Key Features

• MIPI I3C v1.1.1 SDR private write/read — START, address+R/nW, address ACK, one data byte with the I3C T-bit (odd parity, replaces the I²C data-ACK), STOP
• Static 7-bit addressing only — no ENTDAA dynamic address assignment; targets must be provisioned with a fixed address out of band
• No CCC (Common Command Code) engine — broadcast/direct configuration commands (SETMWL, ENEC/DISEC, RSTDAA, etc.) are not issued by this core
• Single fixed controller — no multi-controller bus handoff/arbitration; do not attach a second I3C controller to the bus
• No in-band-interrupt (IBI) or hot-join handling — the FSM never samples sda_in while idle, so IBI-capable targets must have IBI disabled or be serviced off-bus
• Controller-generated SCL via a programmable DIV half-period divisor; open-drain SDA modelled through sda_oe (SDR only — no HDR-DDR/TSP/TSL)
• ASIL-B: config-register parity (err_code 1) + data-register parity (err_code 2) + diverse-DMR FSM/counter/shift lockstep (err_code 9) into one safety_monitor — SPFM 90.75%, LFM 89.23%, PMHF 1.94×10⁻⁹/h

Standards & Compliance

MIPI I3C Specification v1.1.1 (SDR mode, private read/write, static addressing); ISO 26262 ASIL-B SEooC (SPFM 90.75%, LFM 89.23%, PMHF 1.94×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.75% · LFM 89.23% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Getting Started

// Minimal instantiation
i3c_master #(
 .ADDR_W(6)
) u_i3c_master (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.