Serial, Networking & Storage

I3C Target (Slave) Controller

Addressable MIPI I3C target — static-address SDR handshake, ASIL-B lockstep FSM, integration-ready.

Request this IP →Browse the catalog

ASIL-B

target

90.75%

SPFM

89.23%

LFM

PASS

FMEDA

521

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

I3C Target (Slave) Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Addressable MIPI I3C target — static-address SDR handshake, ASIL-B lockstep FSM, integration-ready. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Key Features

Static 7-bit address match against a configurable ADDR register; on-match address ACK (sda_oe low), on-mismatch silent NACK/release — no ENTDAA dynamic-address assignment in v0.1
I3C T-bit data handshake: MSB-first byte plus a 9th transition/parity bit (odd parity) replacing I2C’s per-byte ACK on both the write and read data paths
Host write → RXDATA with RX_READY/irq notification; host read ← TXDATA, shifted out MSB-first followed by the target’s own odd-parity T-bit
No in-band-interrupt (IBI) request and no Common Command Code (CCC) decode in v0.1 — RX_READY/irq is a local APB-domain wire only, not a bus-level attention or broadcast-command response
SCL/SDA double-flopped into clk with START/STOP edge detection; open-drain sda_oe pull-low enable for a shared wired-AND bus (see i3c_link)
Config-register (CTRL/ADDR) even parity into safety_monitor (err_code 1); latched TXDATA/RXDATA data-byte parity (err_code 2)
Diverse complementary-DMR lockstep across the FSM state, bit counter, and RX/TX shift registers, plus duplicated ADDRESSED/RW/RX_READY status-flag and bus-sync shadows (err_code 9)

Standards & Compliance

MIPI I3C (SDR private-transfer subset, static addressing — ENTDAA/CCC/IBI are v0.2+ roadmap); ISO 26262 ASIL-B SEooC (SPFM 90.75%, LFM 89.23%, PMHF 9.08×10⁻¹⁰/h)

Functional Safety

ASIL-B (SEooC) · SPFM 90.75% · LFM 89.23% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN 0x04 ADDR [6:0] 0x08 STATUS [0]=RX_READY [1]=ADDRESSED [2]=RW
`0x0C`	TXDATA	0x10 RXDATA (read clears RX_READY)

Getting Started

// Minimal instantiation
i3c_slave #(
 .ADDR_W(6)
) u_i3c_slave (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in I3C Target (Slave) Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space