Serial, Networking & Storage

ISO/IEC 14443 Contactless Proximity Smart-Card PICC Controller

ISO 14443 card-side (PICC) controller — cascade-level anticollision, T=CL, lockstep-safe.

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ASIL-B

target

91.75%

SPFM

89.80%

LFM

PASS

FMEDA

8.4K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

ISO 14443 card-side (PICC) controller — cascade-level anticollision, T=CL, lockstep-safe. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable ISO/IEC 14443 contactless proximity smart-card PICC-side (the card, not the reader/PCD) controller soft-IP — a responder role, matching the catalog’s established responder/target pattern (iso7816_icc/cxpi_node/smbus_slave) — this IP is the card side; a paired VIP (reader/PCD side, vip-iso14443) is a later, separate effort.

Key Features

REQA/WUPA short-frame wake detection + ATQA response (silent until polled, matching the real spec)
Cascade-level anticollision — NVB/UID-CLn/BCC bit-oriented resolution, single/double/triple UID sizes, up to 3 cascade levels
RATS→ATS — autonomous TL+body+hardware-computed CRC_A transmission
Type B REQB/WUPB (CRC_B-validated before responding)→ATQB (PUPI/AppData/ProtoInfo)→ATTRIB→Answer-to-ATTRIB
Shared T=CL block engine — I/R/S-block classification, real 16-bit CRC_A/CRC_B (not LRC), autonomous R-block NACK + S(WTX) echo
Diverse-DMR lockstep spanning the 15-state PICC FSM, byte engines, wake detector, AND channel-select/cascade-level/halted control state (err_code 9)
Config + datapath register parity, incl. the inbound staging buffer (err_code 1 / 2)

Standards & Compliance

ISO/IEC 14443-3/-4 (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification)

Functional Safety

ASIL-B (SEooC) · SPFM 91.75% · LFM 89.80% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]EN [1]TCL_SUPPORTED [4]RST_START(self-clearing test/diag)
`0x04`	STATUS	RO [0]BUSY [1]FIELD_PRESENT [2]ATQA_DONE [3]ATQB_DONE [4]SAK_DONE [5]SELECTED [6]TCL_ACTIVE [7]TCL_RXDONE [8]TCL_TXD…
`0x08`	BITRATE	RW [15:0] 16x-oversampled bit-period divisor
`0x0C`	UID_SIZE	RW [1:0] 0=single(4B) 1=double(7B) 2=triple(10B)
`0x10`	OWN_UID0	RW [31:0] logical UID bytes 0-3

…5 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
iso14443_picc #(
 .ADDR_W(6)
) u_iso14443_picc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ISO/IEC 14443 Contactless Proximity Smart-Card PICC Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space