RISC-V Cores & SoC Platform

JTAG Debug Transport

A Jtag Dtm peripheral delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

92.75%

SPFM

90.00%

LFM

PASS

FMEDA

1.3K

gates

1.0.0

version

The deliverable

What you’re licensing

A Jtag Dtm peripheral delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

Jtag Dtm — Introduction

    ## What it is

    A Jtag Dtm peripheral delivered as synthesizable SystemVerilog soft-IP. Delivered as synthesizable SystemVerilog on a APB4 slave with
    built-in ASIL B safety instrumentation.

Key Features

16-state TAP FSM + IR (IDCODE/DTMCS/DMI/BYPASS)
DMI register bridge to a Debug Module
tck (\rightarrow) clk 2-FF CDC + lifecycle debug-enable gate
TAP-FSM diverse DMR (err_code 9)
DMI timeout (err_code 4) + IR/protocol checks (err_code 1/3)
Drives a riscv_dm Debug Module

Standards & Compliance

IEEE 1149.1, RISC-V Debug Specification

Functional Safety

ASIL-B (SEooC) · SPFM 92.75% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=dbg_en_soft (ANDed with dbg_en_i) [1]=dmihardreset (W1pulse) [8]=cfg_par
`0x04`	STATUS	[3:0]=tap_state(sys-synced) [5:4]=dmi_op_status [6]=dmi_busy [7]=dbg_active(RO)
`0x08`	IDCODE	[31:0]=IDCODE value (RO)
`0x0C`	IR	[4:0]=captured IR (RO, sys-synced) [8]=ir_par_err(RO)
`0x10`	DMI_ADDR	[ABITS-1:0]=last DMI address (RO)

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
jtag_dtm #(
  .ADDR_W(6)
) u_jtag_dtm (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in JTAG Debug Transport?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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