AI Inference & Acceleration

KVCE-Std

Datacenter-inference KV-cache compression engine: 3-tier hot/warm/cold recency policy with a selectable warm-tier format — INT4 or OCP-Microscaling…

Request this IP →Browse the catalog

ASIL-B

target

91.47%

SPFM

90.00%

LFM

PASS

FMEDA

11.8K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

Datacenter-inference KV-cache compression engine: 3-tier hot/warm/cold recency policy with a selectable warm-tier format — INT4 or OCP-Microscaling… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Datacenter KV-cache compression engine. Extends KVCE-Lite ( AXI engines, page table, bump allocator, BYPASS).

Key Features

3-tier recency policy (kvce_tier_mgr3): hot=native passthrough, warm=INT4 or MXFP4, cold=INT2+Huffman, picked per block from two programmable thresholds (TIER0_LIMIT/TIER1_LIMIT)
Selectable warm-tier format via GROUP_CFG.warm_fmt: INT4 symmetric group-quant (default) or MXFP4 — OCP Microscaling FP4, 4-bit E2M1 element + shared E8M0 block-scale byte, round-to-nearest-even — latched per block in the page table at write time
Cold-tier INT2 group-quant (3.88× vs INT8 / 7.76× vs BF16 at group=128) plus a canonical Huffman entropy codec (per-model APB-loaded code table, table parity feeds err_code 9)
On-chip compressed page table maps logical (seq,layer,block) to physical (offset,length,format) so a hardware DMA addresses variable-ratio compressed blocks with no software bookkeeping
CTRL.BYPASS transparent-AXI escape for bit-exact bring-up before enabling compression; formally bounded round-trip error |x − x̂| ≤ scale for INT4/INT2 (property G1); MXFP4 verified bit-exact RTL-vs-golden (tb_mxfp4 vs tools/kvce_mxfp4_gold.py)
ASIL-B overlay: config even parity (err_code 1), command-FIFO SECDED + pointer-DMR (err_code 2), AXI SLVERR/DECERR + page-table-miss/mem-full/bad-descriptor (err_code 3), command-FSM complementary DMR + Huffman-table parity (err_code 9)
Catalog FMEDA: SPFM 91.47%, LFM 90.00%, PMHF 1.90×10⁻⁸/h — PASS against ASIL-B

Standards & Compliance

AMBA AXI4, AXI4-Stream, APB4; OCP Microscaling (MX) Formats v1.0 (MXFP4/E2M1+E8M0); ISO 26262 ASIL-B SEooC (SPFM 91.47%, LFM 90.00%, PMHF 1.90×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.47% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
kvce_std #(
 .ADDR_W(6)
) u_kvce_std (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Technical paper

The architecture, prior-art positioning, and integration story of this engine are set out in the open-access paper “Inline Hardware KV-Cache Compression for Long-Context Transformer Inference” (Zenodo). Detailed microarchitecture and quantitative sign-off data follow under a mutual NDA.

Interested in KVCE-Std?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space