System, Safety & Compute

STUMPS Logic BIST Controller (lbist)

Key-on/periodic in-field logic-BIST engine that closes the ISO 26262 latent-fault gap for random core logic — ASIL-B SEooC, PASS.

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ASIL-B

target

98.90%

SPFM

100.00%

LFM

Informational

FMEDA

1.0K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

STUMPS Logic BIST Controller (lbist) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Key-on/periodic in-field logic-BIST engine that closes the ISO 26262 latent-fault gap for random core logic — ASIL-B SEooC, PASS. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Lbist — Reference Manual (v0.1.0)

Status: v0.1.0 design specification. This document defines the register map, port list, and behavior implemented in rtl/lbist.sv.

Key Features

STUMPS PRPG/MISR engine: 32-bit LFSR pattern generator (PRPG_POLY) drives scan_in/scan_en into the DUT’s own scan chains; a 32-bit MISR (MISR_POLY) compacts scan_out over a programmed PATTERNS count and compares to GOLDEN
Key-on/periodic scheduling model: a non-concurrent, intrusive test triggered externally (CTRL.start) rather than a free-running timer, so the safety manager controls exactly when the DUT is taken off its mission function
Restartable S_IDLE/S_RUN/S_DONE sequencer; bist_running/bist_done/bist_pass report the DUT verdict, and SIGOUT reads the live signature back so a golden value can be captured during bring-up
Spatial-DMR MISR + complementary-DMR pattern counter — a divergence flags the signature/count engine itself as faulty, err_code 9, so it cannot produce a false pass
Complementary-DMR shadow of the control FSM, checked every cycle, catches a stuck or corrupted sequencer as err_code 3 before it hangs or truncates a run
Even-parity protection over SEED ^ GOLDEN flags a corrupted configuration as err_code 1 before it turns a real DUT fault into a false pass
ASIL-B SEooC, PASS: SPFM 98.90%, LFM 100.00%, PMHF 2.09×10⁻¹⁰/h (catalog FMEDA); APB4 slave register map (CTRL 0x00, SEED 0x04, GOLDEN 0x08, STATUS 0x0C, SIGOUT 0x10) keeps config/status off the scan datapath

Standards & Compliance

ISO 26262 ASIL-B SEooC (SPFM 98.90%, LFM 100.00%, PMHF 2.09×10⁻¹⁰/h) — PASS

Functional Safety

ASIL-B target (SEooC) · SPFM 98.90% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	bit0 = start (self-clearing), bit1 = periodic-enable (status only)
`0x04`	SEED	PRPG seed (LFSR initial value, non-zero)
`0x08`	GOLDEN	expected end-of-run MISR signature
`0x0C`	STATUS	RO [0]=running [1]=done [2]=pass
`0x10`	SIGOUT	RO last MISR signature (read to capture the golden during bring-up)

Getting Started

// Minimal instantiation
lbist #(
 .ADDR_W(6)
) u_lbist (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in STUMPS Logic BIST Controller (lbist)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

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Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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