Serial, Networking & Storage

LIN 2.x Master/Slave Controller

LIN 2.x master/slave body-network controller with automatic baud-rate detection, ASIL-B.

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ASIL-B

target

90.14%

SPFM

99.00%

LFM

PASS

FMEDA

4.2K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

LIN 2.x Master/Slave Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

LIN 2.x master/slave body-network controller with automatic baud-rate detection, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable LIN (Local Interconnect Network) 2.x bus controller delivered as synthesizable SystemVerilog soft-IP, operating as either bus master or slave on an APB4 register interface.

Key Features

LIN 2.x master and slave modes, runtime-selectable via CTRL.MODE — one instance can serve either role on the cluster
Full frame hardware: BREAK, SYNC (0x55), protected identifier (P0/P1 parity), 1-8 data bytes, classic or enhanced checksum
Slave-mode automatic baud-rate detection (ABD_EN) re-measures the SYNC field every frame and rewrites BAUD, tracking a low-precision oscillator with no firmware intervention
Bus-fault detection — checksum, PID parity, framing, timeout, master read-back bit-error, and SAE J2602 collision logging — all aggregated to err_code 3
Even-parity protected config registers (CTRL/BAUD/ID/DLC/ABD_EN) → err_code 1; SECDED-protected receive-data buffer → err_code 2
Complementary-DMR FSM lockstep across the TX, RX, and frame-sequencing engines → err_code 9, feeding the shared safety_monitor
APB4 slave register interface with maskable interrupt (lin_irq); external LIN-transceiver boundary at lin_tx/lin_rx (2-FF synchronized on receive)

Standards & Compliance

LIN 2.x; SAE J2602 collision-detection logging; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 90.14% · LFM 99.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 BAUD 0x0C ID 0x10 DLC
`0x14`	DATA0	0x18 DATA1 0x1C CHECKSUM 0x20 IER 0x24 ISR 0x28 ERR
`0x2C`	ABD_EN

Getting Started

// Minimal instantiation
lin #(
 .ADDR_W(6)
) u_lin (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in LIN 2.x Master/Slave Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space