AI Inference & Acceleration

LM Head

lmhead is the LLM decode sampler (A-6) — the decode last-mile that turns a transformer’s output logit vector into a token,

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ASIL-B

target

96.00%

SPFM

100.00%

LFM

PASS

FMEDA

900

gates

1.0.0

version

The deliverable

What you’re licensing

lmhead is the LLM decode sampler (A-6) — the decode last-mile that turns a transformer’s output logit vector into a token, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

lm_head is the LLM decode sampler (#A-6) — the decode last-mile that turns a transformer’s output logit vector into a token, delivered as synthesizable SystemVerilog soft-IP with an AXI4-Stream logit ingress, an APB4-lite control/status slave, and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

Four modes: argmax / streaming top-k / seeded softmax-sample + temperature scaling
Single-pass, O(k) over the vocab — vocabulary never buffered
Config-register parity over K/temperature/seed (M1 -> err_code 1)
Argmax/top-k monotonic running-max invariant (M2 -> err_code 3)
Diverse-DMR control FSM, shadow stores the state complement (M3 -> err_code 9)

Standards & Compliance

ISO 26262 (ASIL-B), AXI4-Stream + APB4

Functional Safety

ASIL-B (SEooC) · SPFM 96.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [2:1]=MODE (0 argmax/1 topk/2 sample), [7:3]=K (1..MAXK)
`0x04`	TEMP	RW [3:0]=TEMP_LOG2 (temperature = 2^TEMP_LOG2; 0 = no scaling)
`0x08`	SEED	RW [31:0] LFSR seed for SAMPLE mode (nonzero; reloaded at vector start)
`0x0C`	STATUS	RO [0]=DONE, [1]=CFG_ERR, [2]=MAX_ERR, [3]=FSM_ERR, [4]=ERR_VALID, [8:5]=ERR_CODE
`0x10`	TOKEN	RO [LOGIDX_W-1:0] emitted token index (valid when DONE)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
lm_head #(
  .ADDR_W(6)
) u_lm_head (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in LM Head?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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