AI Inference & Acceleration

LM Head — Streaming Decode Sampler (Logits-to-Token)

Single-pass argmax / top-k / sample decode sampler turning transformer logits into a token for on-device edge-AI inference, ASIL-B.

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ASIL-B

target

96.19%

SPFM

100.00%

LFM

Informational

FMEDA

6.5K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

LM Head — Streaming Decode Sampler (Logits-to-Token) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Single-pass argmax / top-k / sample decode sampler turning transformer logits into a token for on-device edge-AI inference, ASIL-B. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

lm_head is the LLM final-projection / logits stage (#A-6) — the decode sampler that turns a transformer’s output logit vector into the next emitted token for on-device edge-AI inference.

Key Features

Single-pass, O(k) streaming over the vocab — a running argmax (O(1)) and an O(k) sorted top-k insertion array mean the full vocabulary is never buffered; area/latency independent of vocab size
Three decode modes over CTRL.MODE: greedy ARGMAX, streaming TOP-K (rank-0 emitted, full k-set readable at TOPK0..), and seeded weighted-reservoir SAMPLE (32-bit Galois LFSR, bit-exact replay for a fixed nonzero SEED)
Monotone temperature scaling (arithmetic right-shift by TEMP_LOG2) ahead of every compare/sample — preserves argmax ordering, so it cannot silently invert the safety invariant
M1 config-register parity over K/temperature/seed -> err_code 1 (STATUS.CFG_ERR)
M4 index/token/running-max duplicate-DMR (KEEP_ATTR shadows) -> err_code 2 (STATUS.TOK_ERR), closing the gap where a stuck-HIGH running max evades the M2 invariant
M2 monotonic running-max invariant (emitted logit must be ≥ every logit seen) -> err_code 3 (STATUS.MAX_ERR); M3 diverse-DMR control FSM (complement shadow) -> err_code 9 (STATUS.FSM_ERR)
AXI4-Stream ingress is always-ready (no backpressure) and APB4-lite carries config/status only — a clean data-plane / config-plane split for integration

Standards & Compliance

AMBA AXI4-Stream logit ingress; APB4-lite control/status slave; ISO 26262 ASIL-B SEooC (SPFM 96.19%, LFM 100.00%, PMHF 4.96×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 96.19% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [2:1]=MODE (0 argmax/1 topk/2 sample), [7:3]=K (1..MAXK)
`0x04`	TEMP	RW [3:0]=TEMP_LOG2 (temperature = 2^TEMP_LOG2; 0 = no scaling)
`0x08`	SEED	RW [31:0] LFSR seed for SAMPLE mode (nonzero; reloaded at vector start)
`0x0C`	STATUS	RO [0]=DONE, [1]=CFG_ERR, [2]=MAX_ERR, [3]=FSM_ERR, [4]=ERR_VALID, [8:5]=ERR_CODE
`0x10`	TOKEN	RO [LOGIDX_W-1:0] emitted token index (valid when DONE)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
lm_head #(
 .ADDR_W(6)
) u_lm_head (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in LM Head — Streaming Decode Sampler (Logits-to-Token)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space